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[198.137.202.9]) by mx.google.com with ESMTPS id w8si9400500igb.83.2015.09.11.02.08.58 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 11 Sep 2015 02:08:58 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-arm-kernel-bounces+patch=linaro.org@lists.infradead.org designates 198.137.202.9 as permitted sender) client-ip=198.137.202.9; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1ZaKI7-0003ru-Sj; Fri, 11 Sep 2015 09:06:43 +0000 Received: from casper.infradead.org ([2001:770:15f::2]) by bombadil.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1ZaK99-0001Dg-PA for linux-arm-kernel@bombadil.infradead.org; Fri, 11 Sep 2015 08:57:27 +0000 Received: from szxga01-in.huawei.com ([58.251.152.64]) by casper.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1ZaK93-0005Zj-0h for linux-arm-kernel@lists.infradead.org; Fri, 11 Sep 2015 08:57:26 +0000 Received: from 172.24.1.47 (EHLO SZXEML423-HUB.china.huawei.com) ([172.24.1.47]) by szxrg01-dlp.huawei.com (MOS 4.3.7-GA FastPath queued) with ESMTP id CUU27145; Fri, 11 Sep 2015 16:55:51 +0800 (CST) Received: from HGHY1Z002260041.china.huawei.com (10.177.16.142) by SZXEML423-HUB.china.huawei.com (10.82.67.154) with Microsoft SMTP Server id 14.3.235.1; Fri, 11 Sep 2015 16:55:41 +0800 From: Shannon Zhao To: Subject: [PATCH v2 03/22] KVM: ARM64: Add offset defines for PMU registers Date: Fri, 11 Sep 2015 16:54:56 +0800 Message-ID: <1441961715-11688-4-git-send-email-zhaoshenglong@huawei.com> X-Mailer: git-send-email 1.9.0.msysgit.0 In-Reply-To: <1441961715-11688-1-git-send-email-zhaoshenglong@huawei.com> References: <1441961715-11688-1-git-send-email-zhaoshenglong@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.177.16.142] X-CFilter-Loop: Reflected X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20150911_095721_890455_DD853599 X-CRM114-Status: GOOD ( 12.79 ) X-Spam-Score: -4.2 (----) X-Spam-Report: SpamAssassin version 3.4.0 on casper.infradead.org summary: Content analysis details: (-4.2 points, 5.0 required) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 RCVD_IN_MSPIKE_H3 RBL: Good reputation (+3) [58.251.152.64 listed in wl.mailspike.net] -2.3 RCVD_IN_DNSWL_MED RBL: Sender listed at http://www.dnswl.org/, medium trust [58.251.152.64 listed in list.dnswl.org] -0.0 SPF_PASS SPF: sender matches SPF record -0.0 T_RP_MATCHES_RCVD Envelope sender domain matches handover relay domain -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1% [score: 0.0000] -0.0 RCVD_IN_MSPIKE_WL Mailspike good senders X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: , List-Help: , List-Subscribe: , Cc: wei@redhat.com, kvm@vger.kernel.org, marc.zyngier@arm.com, will.deacon@arm.com, peter.huangpeng@huawei.com, linux-arm-kernel@lists.infradead.org, zhaoshenglong@huawei.com, alex.bennee@linaro.org, christoffer.dall@linaro.org, shannon.zhao@linaro.org Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patch=linaro.org@lists.infradead.org X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: patch@linaro.org X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.215.47 as permitted sender) smtp.mailfrom=patch+caf_=patchwork-forward=linaro.org@linaro.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 From: Shannon Zhao We are about to trap and emulate acccesses to each PMU register individually. This adds the context offsets for the AArch64 PMU registers and their AArch32 counterparts. Signed-off-by: Shannon Zhao --- arch/arm64/include/asm/kvm_asm.h | 59 +++++++++++++++++++++++++++++++++++----- 1 file changed, 52 insertions(+), 7 deletions(-) diff --git a/arch/arm64/include/asm/kvm_asm.h b/arch/arm64/include/asm/kvm_asm.h index 3c5fe68..3a1df48 100644 --- a/arch/arm64/include/asm/kvm_asm.h +++ b/arch/arm64/include/asm/kvm_asm.h @@ -56,14 +56,36 @@ #define DBGWVR15_EL1 86 #define MDCCINT_EL1 87 /* Monitor Debug Comms Channel Interrupt Enable Reg */ +/* Performance Monitors Registers */ +#define PMCR_EL0 88 /* Control Register */ +#define PMOVSSET_EL0 89 /* Overflow Flag Status Set Register */ +#define PMOVSCLR_EL0 90 /* Overflow Flag Status Clear Register */ +#define PMSELR_EL0 91 /* Event Counter Selection Register */ +#define PMCEID0_EL0 92 /* Common Event Identification Register 0 */ +#define PMCEID1_EL0 93 /* Common Event Identification Register 1 */ +#define PMEVCNTR0_EL0 94 /* Event Counter Register (0-30) */ +#define PMEVCNTR30_EL0 124 +#define PMCCNTR_EL0 125 /* Cycle Counter Register */ +#define PMEVTYPER0_EL0 126 /* Event Type Register (0-30) */ +#define PMEVTYPER30_EL0 156 +#define PMCCFILTR_EL0 157 /* Cycle Count Filter Register */ +#define PMXEVCNTR_EL0 158 /* Selected Event Count Register */ +#define PMXEVTYPER_EL0 159 /* Selected Event Type Register */ +#define PMCNTENSET_EL0 160 /* Count Enable Set Register */ +#define PMCNTENCLR_EL0 161 /* Count Enable Clear Register */ +#define PMINTENSET_EL1 162 /* Interrupt Enable Set Register */ +#define PMINTENCLR_EL1 163 /* Interrupt Enable Clear Register */ +#define PMUSERENR_EL0 164 /* User Enable Register */ +#define PMSWINC_EL0 165 /* Software Increment Register */ + /* 32bit specific registers. Keep them at the end of the range */ -#define DACR32_EL2 88 /* Domain Access Control Register */ -#define IFSR32_EL2 89 /* Instruction Fault Status Register */ -#define FPEXC32_EL2 90 /* Floating-Point Exception Control Register */ -#define DBGVCR32_EL2 91 /* Debug Vector Catch Register */ -#define TEECR32_EL1 92 /* ThumbEE Configuration Register */ -#define TEEHBR32_EL1 93 /* ThumbEE Handler Base Register */ -#define NR_SYS_REGS 94 +#define DACR32_EL2 166 /* Domain Access Control Register */ +#define IFSR32_EL2 167 /* Instruction Fault Status Register */ +#define FPEXC32_EL2 168 /* Floating-Point Exception Control Register */ +#define DBGVCR32_EL2 169 /* Debug Vector Catch Register */ +#define TEECR32_EL1 170 /* ThumbEE Configuration Register */ +#define TEEHBR32_EL1 171 /* ThumbEE Handler Base Register */ +#define NR_SYS_REGS 172 /* 32bit mapping */ #define c0_MPIDR (MPIDR_EL1 * 2) /* MultiProcessor ID Register */ @@ -85,6 +107,24 @@ #define c6_IFAR (c6_DFAR + 1) /* Instruction Fault Address Register */ #define c7_PAR (PAR_EL1 * 2) /* Physical Address Register */ #define c7_PAR_high (c7_PAR + 1) /* PAR top 32 bits */ + +/* Performance Monitors*/ +#define c9_PMCR (PMCR_EL0 * 2) +#define c9_PMOVSSET (PMOVSSET_EL0 * 2) +#define c9_PMOVSCLR (PMOVSCLR_EL0 * 2) +#define c9_PMCCNTR (PMCCNTR_EL0 * 2) +#define c9_PMSELR (PMSELR_EL0 * 2) +#define c9_PMCEID0 (PMCEID0_EL0 * 2) +#define c9_PMCEID1 (PMCEID1_EL0 * 2) +#define c9_PMXEVCNTR (PMXEVCNTR_EL0 * 2) +#define c9_PMXEVTYPER (PMXEVTYPER_EL0 * 2) +#define c9_PMCNTENSET (PMCNTENSET_EL0 * 2) +#define c9_PMCNTENCLR (PMCNTENCLR_EL0 * 2) +#define c9_PMINTENSET (PMINTENSET_EL1 * 2) +#define c9_PMINTENCLR (PMINTENCLR_EL1 * 2) +#define c9_PMUSERENR (PMUSERENR_EL0 * 2) +#define c9_PMSWINC (PMSWINC_EL0 * 2) + #define c10_PRRR (MAIR_EL1 * 2) /* Primary Region Remap Register */ #define c10_NMRR (c10_PRRR + 1) /* Normal Memory Remap Register */ #define c12_VBAR (VBAR_EL1 * 2) /* Vector Base Address Register */ @@ -96,6 +136,11 @@ #define c10_AMAIR1 (c10_AMAIR0 + 1)/* Aux Memory Attr Indirection Reg */ #define c14_CNTKCTL (CNTKCTL_EL1 * 2) /* Timer Control Register (PL1) */ +/* Performance Monitors*/ +#define c14_PMEVCNTR0 (PMEVCNTR0_EL0 * 2) +#define c14_PMEVTYPER0 (PMEVTYPER0_EL0 * 2) +#define c14_PMCCFILTR (PMCCFILTR_EL0 * 2) + #define cp14_DBGDSCRext (MDSCR_EL1 * 2) #define cp14_DBGBCR0 (DBGBCR0_EL1 * 2) #define cp14_DBGBVR0 (DBGBVR0_EL1 * 2)