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[2001:1868:205::9]) by mx.google.com with ESMTPS id tz5si960083pbc.116.2015.09.11.01.59.21 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 11 Sep 2015 01:59:22 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-arm-kernel-bounces+patch=linaro.org@lists.infradead.org designates 2001:1868:205::9 as permitted sender) client-ip=2001:1868:205::9; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1ZaK9n-0001qZ-9c; Fri, 11 Sep 2015 08:58:07 +0000 Received: from merlin.infradead.org ([205.233.59.134]) by bombadil.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1ZaK8z-00013O-Nd for linux-arm-kernel@bombadil.infradead.org; Fri, 11 Sep 2015 08:57:17 +0000 Received: from szxga01-in.huawei.com ([58.251.152.64]) by merlin.infradead.org with esmtps (Exim 4.85 #2 (Red Hat Linux)) id 1ZaK8s-0001YU-PO for linux-arm-kernel@lists.infradead.org; Fri, 11 Sep 2015 08:57:13 +0000 Received: from 172.24.1.48 (EHLO SZXEML423-HUB.china.huawei.com) ([172.24.1.48]) by szxrg01-dlp.huawei.com (MOS 4.3.7-GA FastPath queued) with ESMTP id CUU27174; Fri, 11 Sep 2015 16:55:58 +0800 (CST) Received: from HGHY1Z002260041.china.huawei.com (10.177.16.142) by SZXEML423-HUB.china.huawei.com (10.82.67.154) with Microsoft SMTP Server id 14.3.235.1; Fri, 11 Sep 2015 16:55:48 +0800 From: Shannon Zhao To: Subject: [PATCH v2 12/22] KVM: ARM64: Add reset and access handlers for PMCNTENSET and PMCNTENCLR register Date: Fri, 11 Sep 2015 16:55:05 +0800 Message-ID: <1441961715-11688-13-git-send-email-zhaoshenglong@huawei.com> X-Mailer: git-send-email 1.9.0.msysgit.0 In-Reply-To: <1441961715-11688-1-git-send-email-zhaoshenglong@huawei.com> References: <1441961715-11688-1-git-send-email-zhaoshenglong@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.177.16.142] X-CFilter-Loop: Reflected X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20150911_045711_801149_C1E621A3 X-CRM114-Status: GOOD ( 16.04 ) X-Spam-Score: -4.2 (----) X-Spam-Report: SpamAssassin version 3.4.1 on merlin.infradead.org summary: Content analysis details: (-4.2 points) pts rule name description ---- ---------------------- -------------------------------------------------- -2.3 RCVD_IN_DNSWL_MED RBL: Sender listed at http://www.dnswl.org/, medium trust [58.251.152.64 listed in list.dnswl.org] -0.0 RCVD_IN_MSPIKE_H3 RBL: Good reputation (+3) [58.251.152.64 listed in wl.mailspike.net] -0.0 T_RP_MATCHES_RCVD Envelope sender domain matches handover relay domain -0.0 SPF_PASS SPF: sender matches SPF record -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1% [score: 0.0000] -0.0 RCVD_IN_MSPIKE_WL Mailspike good senders X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: , List-Help: , List-Subscribe: , Cc: wei@redhat.com, kvm@vger.kernel.org, marc.zyngier@arm.com, will.deacon@arm.com, peter.huangpeng@huawei.com, linux-arm-kernel@lists.infradead.org, zhaoshenglong@huawei.com, alex.bennee@linaro.org, christoffer.dall@linaro.org, shannon.zhao@linaro.org Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patch=linaro.org@lists.infradead.org X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: patch@linaro.org X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.215.46 as permitted sender) smtp.mailfrom=patch+caf_=patchwork-forward=linaro.org@linaro.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 From: Shannon Zhao Since the reset value of PMCNTENSET and PMCNTENCLR is UNKNOWN, use reset_unknown for its reset handler. Add a new case to emulate writing PMCNTENSET or PMCNTENCLR register. When writing to PMCNTENSET, call perf_event_enable to enable the perf event. When writing to PMCNTENCLR, call perf_event_disable to disable the perf event. Signed-off-by: Shannon Zhao --- arch/arm64/kvm/sys_regs.c | 46 +++++++++++++++++++++++++++++++++++++++++---- include/kvm/arm_pmu.h | 4 ++++ virt/kvm/arm/pmu.c | 48 +++++++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 94 insertions(+), 4 deletions(-) diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c index f8d7de0..8307189 100644 --- a/arch/arm64/kvm/sys_regs.c +++ b/arch/arm64/kvm/sys_regs.c @@ -293,6 +293,24 @@ static bool access_pmu_regs(struct kvm_vcpu *vcpu, val); break; } + case PMCNTENSET_EL0: { + val = *vcpu_reg(vcpu, p->Rt); + kvm_pmu_enable_counter(vcpu, val); + /*Value 1 of PMCNTENSET_EL0 and PMCNTENCLR_EL0 means + * corresponding counter enabled */ + vcpu_sys_reg(vcpu, r->reg) |= val; + vcpu_sys_reg(vcpu, PMCNTENCLR_EL0) |= val; + break; + } + case PMCNTENCLR_EL0: { + val = *vcpu_reg(vcpu, p->Rt); + kvm_pmu_disable_counter(vcpu, val); + /*Value 0 of PMCNTENSET_EL0 and PMCNTENCLR_EL0 means + * corresponding counter disabled */ + vcpu_sys_reg(vcpu, r->reg) &= ~val; + vcpu_sys_reg(vcpu, PMCNTENSET_EL0) &= ~val; + break; + } case PMCR_EL0: { /* Only update writeable bits of PMCR */ val = vcpu_sys_reg(vcpu, r->reg); @@ -525,10 +543,10 @@ static const struct sys_reg_desc sys_reg_descs[] = { access_pmu_regs, reset_pmcr, PMCR_EL0, }, /* PMCNTENSET_EL0 */ { Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1100), Op2(0b001), - trap_raz_wi }, + access_pmu_regs, reset_unknown, PMCNTENSET_EL0 }, /* PMCNTENCLR_EL0 */ { Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1100), Op2(0b010), - trap_raz_wi }, + access_pmu_regs, reset_unknown, PMCNTENCLR_EL0 }, /* PMOVSCLR_EL0 */ { Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1100), Op2(0b011), trap_raz_wi }, @@ -749,6 +767,24 @@ static bool access_pmu_cp15_regs(struct kvm_vcpu *vcpu, val); break; } + case c9_PMCNTENSET: { + val = *vcpu_reg(vcpu, p->Rt); + kvm_pmu_enable_counter(vcpu, val); + /*Value 1 of PMCNTENSET_EL0 and PMCNTENCLR_EL0 means + * corresponding counter enabled */ + vcpu_cp15(vcpu, r->reg) |= val; + vcpu_cp15(vcpu, c9_PMCNTENCLR) |= val; + break; + } + case c9_PMCNTENCLR: { + val = *vcpu_reg(vcpu, p->Rt); + kvm_pmu_disable_counter(vcpu, val); + /*Value 0 of PMCNTENSET_EL0 and PMCNTENCLR_EL0 means + * corresponding counter disabled */ + vcpu_cp15(vcpu, r->reg) &= ~val; + vcpu_cp15(vcpu, c9_PMCNTENSET) &= ~val; + break; + } case c9_PMCR: { /* Only update writeable bits of PMCR */ val = vcpu_cp15(vcpu, r->reg); @@ -817,8 +853,10 @@ static const struct sys_reg_desc cp15_regs[] = { /* PMU */ { Op1( 0), CRn( 9), CRm(12), Op2( 0), access_pmu_cp15_regs, reset_pmcr, c9_PMCR }, - { Op1( 0), CRn( 9), CRm(12), Op2( 1), trap_raz_wi }, - { Op1( 0), CRn( 9), CRm(12), Op2( 2), trap_raz_wi }, + { Op1( 0), CRn( 9), CRm(12), Op2( 1), access_pmu_cp15_regs, + reset_unknown_cp15, c9_PMCNTENSET }, + { Op1( 0), CRn( 9), CRm(12), Op2( 2), access_pmu_cp15_regs, + reset_unknown_cp15, c9_PMCNTENCLR }, { Op1( 0), CRn( 9), CRm(12), Op2( 3), trap_raz_wi }, { Op1( 0), CRn( 9), CRm(12), Op2( 5), access_pmu_cp15_regs, reset_unknown_cp15, c9_PMSELR }, diff --git a/include/kvm/arm_pmu.h b/include/kvm/arm_pmu.h index 387ec6f..59e70af 100644 --- a/include/kvm/arm_pmu.h +++ b/include/kvm/arm_pmu.h @@ -39,6 +39,8 @@ struct kvm_pmu { #ifdef CONFIG_KVM_ARM_PMU unsigned long kvm_pmu_get_counter_value(struct kvm_vcpu *vcpu, unsigned long select_idx); +void kvm_pmu_disable_counter(struct kvm_vcpu *vcpu, unsigned long val); +void kvm_pmu_enable_counter(struct kvm_vcpu *vcpu, unsigned long val); void kvm_pmu_set_counter_event_type(struct kvm_vcpu *vcpu, unsigned long data, unsigned long select_idx); #else @@ -47,6 +49,8 @@ unsigned long kvm_pmu_get_counter_value(struct kvm_vcpu *vcpu, { return 0; } +void kvm_pmu_disable_counter(struct kvm_vcpu *vcpu, unsigned long val) {} +void kvm_pmu_enable_counter(struct kvm_vcpu *vcpu, unsigned long val) {} void kvm_pmu_set_counter_event_type(struct kvm_vcpu *vcpu, unsigned long data, unsigned long select_idx) {} #endif diff --git a/virt/kvm/arm/pmu.c b/virt/kvm/arm/pmu.c index 0c7fe5c..c6cdc4e 100644 --- a/virt/kvm/arm/pmu.c +++ b/virt/kvm/arm/pmu.c @@ -115,6 +115,54 @@ unsigned long kvm_pmu_get_counter_value(struct kvm_vcpu *vcpu, } /** + * kvm_pmu_enable_counter - enable selected PMU counter + * @vcpu: The vcpu pointer + * @val: the value guest writes to PMCNTENSET register + * + * Call perf_event_enable to start counting the perf event + */ +void kvm_pmu_enable_counter(struct kvm_vcpu *vcpu, unsigned long val) +{ + int i; + struct kvm_pmu *pmu = &vcpu->arch.pmu; + struct kvm_pmc *pmc; + + for (i = 0; i < 32; i++) { + if ((val >> i) & 0x1) { + pmc = &pmu->pmc[i]; + if (pmc->perf_event) { + perf_event_enable(pmc->perf_event); + if (pmc->perf_event->state + != PERF_EVENT_STATE_ACTIVE) + kvm_debug("fail to enable event\n"); + } + } + } +} + +/** + * kvm_pmu_disable_counter - disable selected PMU counter + * @vcpu: The vcpu pointer + * @val: the value guest writes to PMCNTENCLR register + * + * Call perf_event_disable to stop counting the perf event + */ +void kvm_pmu_disable_counter(struct kvm_vcpu *vcpu, unsigned long val) +{ + int i; + struct kvm_pmu *pmu = &vcpu->arch.pmu; + struct kvm_pmc *pmc; + + for (i = 0; i < 32; i++) { + if ((val >> i) & 0x1) { + pmc = &pmu->pmc[i]; + if (pmc->perf_event) + perf_event_disable(pmc->perf_event); + } + } +} + +/** * kvm_pmu_find_hw_event - find hardware event * @pmu: The pmu pointer * @event_select: The number of selected event type