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[64.2.3.194]) by smtp.gmail.com with ESMTPSA id d8sm6393071igl.13.2015.08.29.11.46.29 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sat, 29 Aug 2015 11:46:30 -0700 (PDT) Received: from vmware.wrightpinski.org (localhost [127.0.0.1]) by vmware.wrightpinski.org (8.14.4/8.14.4/Debian-4) with ESMTP id t7TIkPrv044099; Sun, 30 Aug 2015 02:46:25 +0800 Received: (from pinskia@localhost) by vmware.wrightpinski.org (8.14.4/8.14.4/Submit) id t7TIkOMd044098; Sun, 30 Aug 2015 02:46:24 +0800 From: Andrew Pinski To: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, pinskia@gmail.com, apinski@cavium.com Subject: [PATCHv2] ARM64: Add AT_ARM64_MIDR to the aux vector Date: Sun, 30 Aug 2015 02:46:22 +0800 Message-Id: <1440873982-44062-1-git-send-email-apinski@cavium.com> X-Mailer: git-send-email 1.7.10.4 Sender: linux-kernel-owner@vger.kernel.org Precedence: list List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: apinski@cavium.com X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.217.174 as permitted sender) smtp.mailfrom=patch+caf_=patchwork-forward=linaro.org@linaro.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , It is useful to pass down MIDR register down to userland if all of the online cores are all the same type. This adds AT_ARM64_MIDR aux vector type and passes down the midr system register. This is alternative to MIDR_EL1 part of http://lists.infradead.org/pipermail/linux-arm-kernel/2015-July/358995.html. It allows for faster access to midr_el1 than going through a trap and does not exist if the set of cores are not the same. Changes from v1: Forgot to include the auxvec.h part. Signed-off-by: Andrew Pinski --- arch/arm64/include/asm/cpu.h | 1 + arch/arm64/include/asm/elf.h | 6 ++++++ arch/arm64/include/uapi/asm/auxvec.h | 3 +++ arch/arm64/kernel/cpuinfo.c | 22 ++++++++++++++++++++++ 4 files changed, 32 insertions(+) diff --git a/arch/arm64/include/asm/cpu.h b/arch/arm64/include/asm/cpu.h index 8e797b2..fab0aa1 100644 --- a/arch/arm64/include/asm/cpu.h +++ b/arch/arm64/include/asm/cpu.h @@ -62,5 +62,6 @@ DECLARE_PER_CPU(struct cpuinfo_arm64, cpu_data); void cpuinfo_store_cpu(void); void __init cpuinfo_store_boot_cpu(void); +u32 get_arm64_midr(void); #endif /* __ASM_CPU_H */ diff --git a/arch/arm64/include/asm/elf.h b/arch/arm64/include/asm/elf.h index faad6df..d3549de 100644 --- a/arch/arm64/include/asm/elf.h +++ b/arch/arm64/include/asm/elf.h @@ -17,6 +17,7 @@ #define __ASM_ELF_H #include +#include /* * ELF register definitions.. @@ -138,8 +139,13 @@ typedef struct user_fpsimd_state elf_fpregset_t; #define ARCH_DLINFO \ do { \ + u32 midr; \ + \ NEW_AUX_ENT(AT_SYSINFO_EHDR, \ (elf_addr_t)current->mm->context.vdso); \ + midr = get_arm64_midr(); \ + if (midr != 0) \ + NEW_AUX_ENT(AT_ARM64_MIDR, (elf_addr_t)midr); \ } while (0) #define ARCH_HAS_SETUP_ADDITIONAL_PAGES diff --git a/arch/arm64/include/uapi/asm/auxvec.h b/arch/arm64/include/uapi/asm/auxvec.h index 22d6d88..dc55c56 100644 --- a/arch/arm64/include/uapi/asm/auxvec.h +++ b/arch/arm64/include/uapi/asm/auxvec.h @@ -19,4 +19,7 @@ /* vDSO location */ #define AT_SYSINFO_EHDR 33 +/* Machine IDenfier Register (MDIR). */ +#define AT_ARM64_MIDR 38 + #endif diff --git a/arch/arm64/kernel/cpuinfo.c b/arch/arm64/kernel/cpuinfo.c index 75d5a86..b14c87d 100644 --- a/arch/arm64/kernel/cpuinfo.c +++ b/arch/arm64/kernel/cpuinfo.c @@ -254,3 +254,25 @@ void __init cpuinfo_store_boot_cpu(void) boot_cpu_data = *info; } + +u32 get_arm64_midr(void) +{ + int i; + u32 midr = 0; + + for_each_online_cpu(i) { + struct cpuinfo_arm64 *cpuinfo = &per_cpu(cpu_data, i); + u32 oldmidr = midr; + + midr = cpuinfo->reg_midr; + /* + * If there are cpus which have a different + * midr just return 0. + */ + if (oldmidr && oldmidr != midr) + return 0; + } + + return midr; +} +