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[2001:1868:205::9]) by mx.google.com with ESMTPS id ej6si33246657pdb.56.2015.08.10.06.36.59 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 10 Aug 2015 06:36:59 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-arm-kernel-bounces+patch=linaro.org@lists.infradead.org designates 2001:1868:205::9 as permitted sender) client-ip=2001:1868:205::9; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1ZOnEh-0007yX-2R; Mon, 10 Aug 2015 13:35:31 +0000 Received: from mail-pa0-f43.google.com ([209.85.220.43]) by bombadil.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1ZOn8s-00089P-OH for linux-arm-kernel@lists.infradead.org; Mon, 10 Aug 2015 13:29:35 +0000 Received: by pabyb7 with SMTP id yb7so106861774pab.0 for ; Mon, 10 Aug 2015 06:29:10 -0700 (PDT) X-Received: by 10.68.254.136 with SMTP id ai8mr4401887pbd.98.1439213350060; Mon, 10 Aug 2015 06:29:10 -0700 (PDT) Received: from localhost ([199.168.112.128]) by smtp.gmail.com with ESMTPSA id i10sm20024632pdr.78.2015.08.10.06.29.05 (version=TLSv1 cipher=RC4-SHA bits=128/128); Mon, 10 Aug 2015 06:29:09 -0700 (PDT) From: Zhichao Huang To: kvm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, kvmarm@lists.cs.columbia.edu, christoffer.dall@linaro.org, marc.zyngier@arm.com, alex.bennee@linaro.org, will.deacon@arm.com Subject: [PATCH v4 14/15] KVM: arm: implement lazy world switch for debug registers Date: Mon, 10 Aug 2015 21:26:06 +0800 Message-Id: <1439213167-8988-15-git-send-email-zhichao.huang@linaro.org> X-Mailer: git-send-email 1.9.5.msysgit.1 In-Reply-To: <1439213167-8988-1-git-send-email-zhichao.huang@linaro.org> References: <1439213167-8988-1-git-send-email-zhichao.huang@linaro.org> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20150810_062931_303660_187C53A5 X-CRM114-Status: GOOD ( 10.00 ) X-Spam-Score: -2.6 (--) X-Spam-Report: SpamAssassin version 3.4.0 on bombadil.infradead.org summary: Content analysis details: (-2.6 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.7 RCVD_IN_DNSWL_LOW RBL: Sender listed at http://www.dnswl.org/, low trust [209.85.220.43 listed in list.dnswl.org] -0.0 RCVD_IN_MSPIKE_H2 RBL: Average reputation (+2) [209.85.220.43 listed in wl.mailspike.net] -0.0 SPF_PASS SPF: sender matches SPF record -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1% [score: 0.0000] X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: , List-Help: , List-Subscribe: , Cc: huangzhichao@huawei.com, Zhichao Huang MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patch=linaro.org@lists.infradead.org X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: zhichao.huang@linaro.org X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.217.178 as permitted sender) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 Avoid world-switching all the debug registers when neither the host nor the guest has configured any [WB]points. Signed-off-by: Zhichao Huang --- arch/arm/kvm/interrupts_head.S | 23 +++++++++++++++++++++-- 1 file changed, 21 insertions(+), 2 deletions(-) diff --git a/arch/arm/kvm/interrupts_head.S b/arch/arm/kvm/interrupts_head.S index b9e7410..7ad0adf 100644 --- a/arch/arm/kvm/interrupts_head.S +++ b/arch/arm/kvm/interrupts_head.S @@ -332,6 +332,21 @@ vcpu .req r0 @ vcpu pointer always in r0 sub r12, r2, r12 @ How many WPs to skip .endm +/* If VCPU_DEBUG_FLAGS is not set, it means that neither the host + * nor the guest has configured any [WB]points. + * + * We avoid world-switching all the debug registers in that case. + * + * Assume vcpu pointer in vcpu reg + * + * clobbers r2 + */ +.macro skip_debug_state target + ldr r2, [vcpu, #VCPU_DEBUG_FLAGS] + cmp r2, #0 + beq \target +.endm + /* Reads cp14 registers from hardware. * Writes cp14 registers in-order to the CP14 struct pointed to by r10 * @@ -340,12 +355,14 @@ vcpu .req r0 @ vcpu pointer always in r0 * Clobbers r2-r12 */ .macro save_debug_state + skip_debug_state 9999f + read_hw_dbg_num cp14_read_and_str r10, 4, cp14_DBGBVR0, r11 cp14_read_and_str r10, 5, cp14_DBGBCR0, r11 cp14_read_and_str r10, 6, cp14_DBGWVR0, r12 cp14_read_and_str r10, 7, cp14_DBGWCR0, r12 - +9999: /* DBGDSCR reg */ mrc p14, 0, r2, c0, c1, 0 str r2, [r10, #CP14_OFFSET(cp14_DBGDSCRext)] @@ -359,12 +376,14 @@ vcpu .req r0 @ vcpu pointer always in r0 * Clobbers r2-r12 */ .macro restore_debug_state + skip_debug_state 9999f + read_hw_dbg_num cp14_ldr_and_write r10, 4, cp14_DBGBVR0, r11 cp14_ldr_and_write r10, 5, cp14_DBGBCR0, r11 cp14_ldr_and_write r10, 6, cp14_DBGWVR0, r12 cp14_ldr_and_write r10, 7, cp14_DBGWCR0, r12 - +9999: /* DBGDSCR reg */ ldr r2, [r10, #CP14_OFFSET(cp14_DBGDSCRext)] mcr p14, 0, r2, c0, c2, 2