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[2001:1868:205::9]) by mx.google.com with ESMTPS id dg8si15528979pac.6.2015.08.10.06.36.20 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 10 Aug 2015 06:36:21 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-arm-kernel-bounces+patch=linaro.org@lists.infradead.org designates 2001:1868:205::9 as permitted sender) client-ip=2001:1868:205::9; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1ZOnE6-0006OG-CH; Mon, 10 Aug 2015 13:34:54 +0000 Received: from mail-pa0-f42.google.com ([209.85.220.42]) by bombadil.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1ZOn8R-0007kj-DY for linux-arm-kernel@lists.infradead.org; Mon, 10 Aug 2015 13:29:11 +0000 Received: by pawu10 with SMTP id u10so140698046paw.1 for ; Mon, 10 Aug 2015 06:28:42 -0700 (PDT) X-Received: by 10.66.55.41 with SMTP id o9mr44184602pap.148.1439213322293; Mon, 10 Aug 2015 06:28:42 -0700 (PDT) Received: from localhost ([199.168.112.128]) by smtp.gmail.com with ESMTPSA id hz5sm19974296pbb.39.2015.08.10.06.28.29 (version=TLSv1 cipher=RC4-SHA bits=128/128); Mon, 10 Aug 2015 06:28:41 -0700 (PDT) From: Zhichao Huang To: kvm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, kvmarm@lists.cs.columbia.edu, christoffer.dall@linaro.org, marc.zyngier@arm.com, alex.bennee@linaro.org, will.deacon@arm.com Subject: [PATCH v4 11/15] KVM: arm: add a function to keep track of host use of the debug registers Date: Mon, 10 Aug 2015 21:26:03 +0800 Message-Id: <1439213167-8988-12-git-send-email-zhichao.huang@linaro.org> X-Mailer: git-send-email 1.9.5.msysgit.1 In-Reply-To: <1439213167-8988-1-git-send-email-zhichao.huang@linaro.org> References: <1439213167-8988-1-git-send-email-zhichao.huang@linaro.org> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20150810_062904_082831_3542101D X-CRM114-Status: GOOD ( 11.62 ) X-Spam-Score: -2.6 (--) X-Spam-Report: SpamAssassin version 3.4.0 on bombadil.infradead.org summary: Content analysis details: (-2.6 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.7 RCVD_IN_DNSWL_LOW RBL: Sender listed at http://www.dnswl.org/, low trust [209.85.220.42 listed in list.dnswl.org] -0.0 RCVD_IN_MSPIKE_H3 RBL: Good reputation (+3) [209.85.220.42 listed in wl.mailspike.net] -0.0 SPF_PASS SPF: sender matches SPF record -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1% [score: 0.0000] -0.0 RCVD_IN_MSPIKE_WL Mailspike good senders X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: , List-Help: , List-Subscribe: , Cc: huangzhichao@huawei.com, Zhichao Huang MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patch=linaro.org@lists.infradead.org X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: zhichao.huang@linaro.org X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.215.53 as permitted sender) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 As we're about to implement a lazy world switch for debug registers, we add a function reading the break/watch control variables directly to indicate whether the host has enabled any break/watch points or not. Signed-off-by: Zhichao Huang --- arch/arm/include/asm/hw_breakpoint.h | 5 +++++ arch/arm/kernel/hw_breakpoint.c | 21 +++++++++++++++++++++ 2 files changed, 26 insertions(+) diff --git a/arch/arm/include/asm/hw_breakpoint.h b/arch/arm/include/asm/hw_breakpoint.h index f2f4c61..6f375c5 100644 --- a/arch/arm/include/asm/hw_breakpoint.h +++ b/arch/arm/include/asm/hw_breakpoint.h @@ -66,9 +66,14 @@ int arch_install_hw_breakpoint(struct perf_event *bp); void arch_uninstall_hw_breakpoint(struct perf_event *bp); void hw_breakpoint_pmu_read(struct perf_event *bp); int hw_breakpoint_slots(int type); +bool hw_breakpoint_enabled(void); #else static inline void clear_ptrace_hw_breakpoint(struct task_struct *tsk) {} +static inline bool hw_breakpoint_enabled(void) +{ + return false; +} #endif /* CONFIG_HAVE_HW_BREAKPOINT */ #endif /* __ASSEMBLY */ diff --git a/arch/arm/kernel/hw_breakpoint.c b/arch/arm/kernel/hw_breakpoint.c index dc7d0a9..f56788f 100644 --- a/arch/arm/kernel/hw_breakpoint.c +++ b/arch/arm/kernel/hw_breakpoint.c @@ -227,6 +227,27 @@ static int get_num_brps(void) return core_has_mismatch_brps() ? brps - 1 : brps; } +/* Indicate whether the host has enabled any break/watch points or not. */ +bool hw_breakpoint_enabled(void) +{ + struct perf_event **slots; + int i; + + slots = this_cpu_ptr(bp_on_reg); + for (i = 0; i < core_num_brps; i++) { + if (slots[i]) + return true; + } + + slots = this_cpu_ptr(wp_on_reg); + for (i = 0; i < core_num_wrps; i++) { + if (slots[i]) + return true; + } + + return false; +} + /* * In order to access the breakpoint/watchpoint control registers, * we must be running in debug monitor mode. Unfortunately, we can