From patchwork Mon Aug 10 13:26:02 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Zhichao Huang X-Patchwork-Id: 52261 Return-Path: X-Original-To: linaro@patches.linaro.org Delivered-To: linaro@patches.linaro.org Received: from mail-la0-f71.google.com (mail-la0-f71.google.com [209.85.215.71]) by patches.linaro.org (Postfix) with ESMTPS id AA1AE22919 for ; Mon, 10 Aug 2015 13:35:53 +0000 (UTC) Received: by lagz9 with SMTP id z9sf42490456lag.3 for ; Mon, 10 Aug 2015 06:35:52 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:delivered-to:from:to:subject:date:message-id :in-reply-to:references:precedence:list-id:list-unsubscribe :list-archive:list-post:list-help:list-subscribe:cc:mime-version :content-type:content-transfer-encoding:sender:errors-to :x-original-sender:x-original-authentication-results:mailing-list; bh=UX0/XeILIW6+rXxkPHAOhd1puIGxZI/ODFJ/E4lQvAk=; b=i1YoeGkR3nf/0sMew5/uhUud2NnmPN+WaqGnfm2h+8y87sJ1wtAJSjjT2VDDM0pSbW ebrQfRf7SFhRXgATnTwa9/EovWtNaYtjbTmo6ysTaZzMIwqq5DBe+/oNIp+06xpxv8dT cXkWDeQCtROyVA0dt/TWTx1F9qpkX9H1oYzz/Mumlq24G040nOOYRnGHKZM/q6LlzwBV EnJbY9t8hRLTPq43EePMWgSSqd7naESHjBB/di27SAjxo+DpxFNpfFSFou7sLlzIavy6 gn6Y7TLx0GaycuWMO8HqflqNDdBbdYaS62IRZKuf0XyC9gz8VX0BicOObr9Ui+fBUi/T MtYA== X-Gm-Message-State: ALoCoQlqCHc/kNmm6lTUkMlQdoynZ9r6qOks714y66sM0QDPms85V8IKrh5PXYb3gyYBYqHJO5Zk X-Received: by 10.180.75.49 with SMTP id z17mr3735722wiv.7.1439213752345; Mon, 10 Aug 2015 06:35:52 -0700 (PDT) X-BeenThere: patchwork-forward@linaro.org Received: by 10.152.242.131 with SMTP id wq3ls587641lac.106.gmail; Mon, 10 Aug 2015 06:35:52 -0700 (PDT) X-Received: by 10.152.204.196 with SMTP id la4mr20273337lac.124.1439213752183; Mon, 10 Aug 2015 06:35:52 -0700 (PDT) Received: from mail-la0-f44.google.com (mail-la0-f44.google.com. [209.85.215.44]) by mx.google.com with ESMTPS id l2si14065082lag.12.2015.08.10.06.35.51 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 10 Aug 2015 06:35:51 -0700 (PDT) Received-SPF: pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.215.44 as permitted sender) client-ip=209.85.215.44; Received: by lahi9 with SMTP id i9so23284516lah.2 for ; Mon, 10 Aug 2015 06:35:51 -0700 (PDT) X-Received: by 10.112.166.2 with SMTP id zc2mr19925185lbb.29.1439213751852; Mon, 10 Aug 2015 06:35:51 -0700 (PDT) X-Forwarded-To: patchwork-forward@linaro.org X-Forwarded-For: patch@linaro.org patchwork-forward@linaro.org Delivered-To: patch@linaro.org Received: by 10.112.7.198 with SMTP id l6csp1938993lba; Mon, 10 Aug 2015 06:35:50 -0700 (PDT) X-Received: by 10.68.142.200 with SMTP id ry8mr44140072pbb.136.1439213750408; Mon, 10 Aug 2015 06:35:50 -0700 (PDT) Received: from bombadil.infradead.org (bombadil.infradead.org. [2001:1868:205::9]) by mx.google.com with ESMTPS id t9si14355513pas.186.2015.08.10.06.35.49 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 10 Aug 2015 06:35:50 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-arm-kernel-bounces+patch=linaro.org@lists.infradead.org designates 2001:1868:205::9 as permitted sender) client-ip=2001:1868:205::9; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1ZOnDX-0005rj-N2; Mon, 10 Aug 2015 13:34:19 +0000 Received: from mail-pa0-f44.google.com ([209.85.220.44]) by bombadil.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1ZOn86-0007R8-NS for linux-arm-kernel@lists.infradead.org; Mon, 10 Aug 2015 13:29:08 +0000 Received: by pacrr5 with SMTP id rr5so104063448pac.3 for ; Mon, 10 Aug 2015 06:28:21 -0700 (PDT) X-Received: by 10.68.248.102 with SMTP id yl6mr45009001pbc.66.1439213301370; Mon, 10 Aug 2015 06:28:21 -0700 (PDT) Received: from localhost ([199.168.112.128]) by smtp.gmail.com with ESMTPSA id ob4sm19975424pbb.40.2015.08.10.06.28.18 (version=TLSv1 cipher=RC4-SHA bits=128/128); Mon, 10 Aug 2015 06:28:20 -0700 (PDT) From: Zhichao Huang To: kvm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, kvmarm@lists.cs.columbia.edu, christoffer.dall@linaro.org, marc.zyngier@arm.com, alex.bennee@linaro.org, will.deacon@arm.com Subject: [PATCH v4 10/15] KVM: arm: implement world switch for debug registers Date: Mon, 10 Aug 2015 21:26:02 +0800 Message-Id: <1439213167-8988-11-git-send-email-zhichao.huang@linaro.org> X-Mailer: git-send-email 1.9.5.msysgit.1 In-Reply-To: <1439213167-8988-1-git-send-email-zhichao.huang@linaro.org> References: <1439213167-8988-1-git-send-email-zhichao.huang@linaro.org> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20150810_062843_334328_E7781750 X-CRM114-Status: GOOD ( 11.77 ) X-Spam-Score: -2.6 (--) X-Spam-Report: SpamAssassin version 3.4.0 on bombadil.infradead.org summary: Content analysis details: (-2.6 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.7 RCVD_IN_DNSWL_LOW RBL: Sender listed at http://www.dnswl.org/, low trust [209.85.220.44 listed in list.dnswl.org] -0.0 RCVD_IN_MSPIKE_H2 RBL: Average reputation (+2) [209.85.220.44 listed in wl.mailspike.net] -0.0 SPF_PASS SPF: sender matches SPF record -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1% [score: 0.0000] X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: , List-Help: , List-Subscribe: , Cc: huangzhichao@huawei.com, Zhichao Huang MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patch=linaro.org@lists.infradead.org X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: zhichao.huang@linaro.org X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.215.44 as permitted sender) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 Implement switching of the debug registers. While the number of registers is massive, CPUs usually don't implement them all (A15 has 6 breakpoints and 4 watchpoints, which gives us a total of 22 registers "only"). Signed-off-by: Zhichao Huang --- arch/arm/kvm/interrupts_head.S | 170 ++++++++++++++++++++++++++++++++++++++--- 1 file changed, 159 insertions(+), 11 deletions(-) diff --git a/arch/arm/kvm/interrupts_head.S b/arch/arm/kvm/interrupts_head.S index 7ac5e51..b9e7410 100644 --- a/arch/arm/kvm/interrupts_head.S +++ b/arch/arm/kvm/interrupts_head.S @@ -5,6 +5,7 @@ #define VCPU_USR_SP (VCPU_USR_REG(13)) #define VCPU_USR_LR (VCPU_USR_REG(14)) #define CP15_OFFSET(_cp15_reg_idx) (VCPU_CP15 + (_cp15_reg_idx * 4)) +#define CP14_OFFSET(_cp14_reg_idx) ((_cp14_reg_idx) * 4) /* * Many of these macros need to access the VCPU structure, which is always @@ -239,6 +240,136 @@ vcpu .req r0 @ vcpu pointer always in r0 save_guest_regs_mode irq, #VCPU_IRQ_REGS .endm +/* Assume r10/r11/r12 are in use, clobbers r2-r3 */ +.macro cp14_read_and_str base Op2 cp14_reg0 skip_num + adr r3, 1f + add r3, r3, \skip_num, lsl #3 + bx r3 +1: + mrc p14, 0, r2, c0, c15, \Op2 + str r2, [\base, #CP14_OFFSET(\cp14_reg0+15)] + mrc p14, 0, r2, c0, c14, \Op2 + str r2, [\base, #CP14_OFFSET(\cp14_reg0+14)] + mrc p14, 0, r2, c0, c13, \Op2 + str r2, [\base, #CP14_OFFSET(\cp14_reg0+13)] + mrc p14, 0, r2, c0, c12, \Op2 + str r2, [\base, #CP14_OFFSET(\cp14_reg0+12)] + mrc p14, 0, r2, c0, c11, \Op2 + str r2, [\base, #CP14_OFFSET(\cp14_reg0+11)] + mrc p14, 0, r2, c0, c10, \Op2 + str r2, [\base, #CP14_OFFSET(\cp14_reg0+10)] + mrc p14, 0, r2, c0, c9, \Op2 + str r2, [\base, #CP14_OFFSET(\cp14_reg0+9)] + mrc p14, 0, r2, c0, c8, \Op2 + str r2, [\base, #CP14_OFFSET(\cp14_reg0+8)] + mrc p14, 0, r2, c0, c7, \Op2 + str r2, [\base, #CP14_OFFSET(\cp14_reg0+7)] + mrc p14, 0, r2, c0, c6, \Op2 + str r2, [\base, #CP14_OFFSET(\cp14_reg0+6)] + mrc p14, 0, r2, c0, c5, \Op2 + str r2, [\base, #CP14_OFFSET(\cp14_reg0+5)] + mrc p14, 0, r2, c0, c4, \Op2 + str r2, [\base, #CP14_OFFSET(\cp14_reg0+4)] + mrc p14, 0, r2, c0, c3, \Op2 + str r2, [\base, #CP14_OFFSET(\cp14_reg0+3)] + mrc p14, 0, r2, c0, c2, \Op2 + str r2, [\base, #CP14_OFFSET(\cp14_reg0+2)] + mrc p14, 0, r2, c0, c1, \Op2 + str r2, [\base, #CP14_OFFSET(\cp14_reg0+1)] + mrc p14, 0, r2, c0, c0, \Op2 + str r2, [\base, #CP14_OFFSET(\cp14_reg0)] +.endm + +/* Assume r11/r12 are in use, clobbers r2-r3 */ +.macro cp14_ldr_and_write base Op2 cp14_reg0 skip_num + adr r3, 1f + add r3, r3, \skip_num, lsl #3 + bx r3 +1: + ldr r2, [\base, #CP14_OFFSET(\cp14_reg0+15)] + mcr p14, 0, r2, c0, c15, \Op2 + ldr r2, [\base, #CP14_OFFSET(\cp14_reg0+14)] + mcr p14, 0, r2, c0, c14, \Op2 + ldr r2, [\base, #CP14_OFFSET(\cp14_reg0+13)] + mcr p14, 0, r2, c0, c13, \Op2 + ldr r2, [\base, #CP14_OFFSET(\cp14_reg0+12)] + mcr p14, 0, r2, c0, c12, \Op2 + ldr r2, [\base, #CP14_OFFSET(\cp14_reg0+11)] + mcr p14, 0, r2, c0, c11, \Op2 + ldr r2, [\base, #CP14_OFFSET(\cp14_reg0+10)] + mcr p14, 0, r2, c0, c10, \Op2 + ldr r2, [\base, #CP14_OFFSET(\cp14_reg0+9)] + mcr p14, 0, r2, c0, c9, \Op2 + ldr r2, [\base, #CP14_OFFSET(\cp14_reg0+8)] + mcr p14, 0, r2, c0, c8, \Op2 + ldr r2, [\base, #CP14_OFFSET(\cp14_reg0+7)] + mcr p14, 0, r2, c0, c7, \Op2 + ldr r2, [\base, #CP14_OFFSET(\cp14_reg0+6)] + mcr p14, 0, r2, c0, c6, \Op2 + ldr r2, [\base, #CP14_OFFSET(\cp14_reg0+5)] + mcr p14, 0, r2, c0, c5, \Op2 + ldr r2, [\base, #CP14_OFFSET(\cp14_reg0+4)] + mcr p14, 0, r2, c0, c4, \Op2 + ldr r2, [\base, #CP14_OFFSET(\cp14_reg0+3)] + mcr p14, 0, r2, c0, c3, \Op2 + ldr r2, [\base, #CP14_OFFSET(\cp14_reg0+2)] + mcr p14, 0, r2, c0, c2, \Op2 + ldr r2, [\base, #CP14_OFFSET(\cp14_reg0+1)] + mcr p14, 0, r2, c0, c1, \Op2 + ldr r2, [\base, #CP14_OFFSET(\cp14_reg0)] + mcr p14, 0, r2, c0, c0, \Op2 +.endm + +/* Get extract number of BRPs and WRPs. Saved in r11/r12 */ +.macro read_hw_dbg_num + mrc p14, 0, r2, c0, c0, 0 + ubfx r11, r2, #24, #4 + add r11, r11, #1 @ Extract BRPs + ubfx r12, r2, #28, #4 + add r12, r12, #1 @ Extract WRPs + mov r2, #16 + sub r11, r2, r11 @ How many BPs to skip + sub r12, r2, r12 @ How many WPs to skip +.endm + +/* Reads cp14 registers from hardware. + * Writes cp14 registers in-order to the CP14 struct pointed to by r10 + * + * Assumes vcpu pointer in vcpu reg + * + * Clobbers r2-r12 + */ +.macro save_debug_state + read_hw_dbg_num + cp14_read_and_str r10, 4, cp14_DBGBVR0, r11 + cp14_read_and_str r10, 5, cp14_DBGBCR0, r11 + cp14_read_and_str r10, 6, cp14_DBGWVR0, r12 + cp14_read_and_str r10, 7, cp14_DBGWCR0, r12 + + /* DBGDSCR reg */ + mrc p14, 0, r2, c0, c1, 0 + str r2, [r10, #CP14_OFFSET(cp14_DBGDSCRext)] +.endm + +/* Reads cp14 registers in-order from the CP14 struct pointed to by r10 + * Writes cp14 registers to hardware. + * + * Assumes vcpu pointer in vcpu reg + * + * Clobbers r2-r12 + */ +.macro restore_debug_state + read_hw_dbg_num + cp14_ldr_and_write r10, 4, cp14_DBGBVR0, r11 + cp14_ldr_and_write r10, 5, cp14_DBGBCR0, r11 + cp14_ldr_and_write r10, 6, cp14_DBGWVR0, r12 + cp14_ldr_and_write r10, 7, cp14_DBGWCR0, r12 + + /* DBGDSCR reg */ + ldr r2, [r10, #CP14_OFFSET(cp14_DBGDSCRext)] + mcr p14, 0, r2, c0, c2, 2 +.endm + /* Reads cp14/cp15 registers from hardware and stores them in memory * @store_to_vcpu: If 0, registers are written in-order to the stack, * otherwise to the VCPU struct pointed to by vcpup @@ -248,11 +379,17 @@ vcpu .req r0 @ vcpu pointer always in r0 * Clobbers r2 - r12 */ .macro read_coproc_state store_to_vcpu - .if \store_to_vcpu == 0 - mrc p14, 0, r2, c0, c1, 0 @ DBGDSCR - push {r2} + .if \store_to_vcpu == 1 + add r10, vcpu, #VCPU_CP14 + .else + add r10, vcpu, #VCPU_HOST_CONTEXT + ldr r10, [r10] + add r10, r10, #VCPU_CP14_HOST .endif + /* Assumes r10 pointer in cp14 regs */ + bl __save_debug_state + mrc p15, 0, r2, c1, c0, 0 @ SCTLR mrc p15, 0, r3, c1, c0, 2 @ CPACR mrc p15, 0, r4, c2, c0, 2 @ TTBCR @@ -331,6 +468,17 @@ vcpu .req r0 @ vcpu pointer always in r0 * Assumes vcpu pointer in vcpu reg */ .macro write_coproc_state read_from_vcpu + .if \read_from_vcpu == 1 + add r10, vcpu, #VCPU_CP14 + .else + add r10, vcpu, #VCPU_HOST_CONTEXT + ldr r10, [r10] + add r10, r10, #VCPU_CP14_HOST + .endif + + /* Assumes r10 pointer in cp14 regs */ + bl __restore_debug_state + .if \read_from_vcpu == 0 pop {r2,r4-r7} .else @@ -399,14 +547,6 @@ vcpu .req r0 @ vcpu pointer always in r0 mcr p15, 0, r10, c10, c2, 0 @ PRRR mcr p15, 0, r11, c10, c2, 1 @ NMRR mcr p15, 2, r12, c0, c0, 0 @ CSSELR - - .if \read_from_vcpu == 0 - pop {r2} - .else - mov r2, #0 - .endif - - mcr p14, 0, r2, c0, c2, 2 @ DBGDSCR .endm /* @@ -657,3 +797,11 @@ ARM_BE8(rev r6, r6 ) .macro load_vcpu mrc p15, 4, vcpu, c13, c0, 2 @ HTPIDR .endm + +__save_debug_state: + save_debug_state + bx lr + +__restore_debug_state: + restore_debug_state + bx lr