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[209.132.180.67]) by mx.google.com with ESMTP id d5si10954264pde.239.2015.07.31.08.38.55; Fri, 31 Jul 2015 08:38:56 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754639AbbGaPiy (ORCPT + 28 others); Fri, 31 Jul 2015 11:38:54 -0400 Received: from mail-pd0-f170.google.com ([209.85.192.170]:36478 "EHLO mail-pd0-f170.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754154AbbGaPh7 (ORCPT ); Fri, 31 Jul 2015 11:37:59 -0400 Received: by pdjr16 with SMTP id r16so45611191pdj.3 for ; Fri, 31 Jul 2015 08:37:59 -0700 (PDT) X-Received: by 10.70.42.202 with SMTP id q10mr8048431pdl.41.1438357079091; Fri, 31 Jul 2015 08:37:59 -0700 (PDT) Received: from t430.cg.shawcable.net ([184.64.168.246]) by smtp.gmail.com with ESMTPSA id y2sm8317284pdi.80.2015.07.31.08.37.58 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 31 Jul 2015 08:37:58 -0700 (PDT) From: Mathieu Poirier To: gregkh@linuxfoundation.org Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, mathieu.poirier@linaro.org Subject: [PATCH 07/10] coresight-etm3x: Support context-ID tracing when PID namespace is enabled Date: Fri, 31 Jul 2015 09:37:27 -0600 Message-Id: <1438357050-22486-8-git-send-email-mathieu.poirier@linaro.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1438357050-22486-1-git-send-email-mathieu.poirier@linaro.org> References: <1438357050-22486-1-git-send-email-mathieu.poirier@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: list List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: mathieu.poirier@linaro.org X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.217.179 as permitted sender) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , From: Chunyan Zhang The Coresight ETM drivers already support context-ID tracing, but it won't work when PID namespace is enabled. This is because when using PID namespace a process id (ie. VPID) seen from the current namespace differs from the id (ie. PID) seen by kernel. So when users write the process id seen by themselves to ETM, there needs to be a translation from VPID to PID, as such ETM drivers will write the PID into the Context ID register correctly. Signed-off-by: Chunyan Zhang Signed-off-by: Mathieu Poirier --- drivers/hwtracing/coresight/coresight-etm.h | 3 +++ drivers/hwtracing/coresight/coresight-etm3x.c | 16 +++++++++++----- 2 files changed, 14 insertions(+), 5 deletions(-) diff --git a/drivers/hwtracing/coresight/coresight-etm.h b/drivers/hwtracing/coresight/coresight-etm.h index 52af5f0adbed..b4481eb29304 100644 --- a/drivers/hwtracing/coresight/coresight-etm.h +++ b/drivers/hwtracing/coresight/coresight-etm.h @@ -184,6 +184,8 @@ * @seq_curr_state: current value of the sequencer register. * @ctxid_idx: index for the context ID registers. * @ctxid_pid: value for the context ID to trigger on. + * @ctxid_vpid: Virtual PID seen by users if PID namespace is enabled, otherwise + * the same value of ctxid_pid. * @ctxid_mask: mask applicable to all the context IDs. * @sync_freq: Synchronisation frequency. * @timestamp_event: Defines an event that requests the insertion @@ -236,6 +238,7 @@ struct etm_drvdata { u32 seq_curr_state; u8 ctxid_idx; u32 ctxid_pid[ETM_MAX_CTXID_CMP]; + u32 ctxid_vpid[ETM_MAX_CTXID_CMP]; u32 ctxid_mask; u32 sync_freq; u32 timestamp_event; diff --git a/drivers/hwtracing/coresight/coresight-etm3x.c b/drivers/hwtracing/coresight/coresight-etm3x.c index 361b82068dda..bf2476ed9356 100644 --- a/drivers/hwtracing/coresight/coresight-etm3x.c +++ b/drivers/hwtracing/coresight/coresight-etm3x.c @@ -237,8 +237,11 @@ static void etm_set_default(struct etm_drvdata *drvdata) drvdata->seq_curr_state = 0x0; drvdata->ctxid_idx = 0x0; - for (i = 0; i < drvdata->nr_ctxid_cmp; i++) + for (i = 0; i < drvdata->nr_ctxid_cmp; i++) { drvdata->ctxid_pid[i] = 0x0; + drvdata->ctxid_vpid[i] = 0x0; + } + drvdata->ctxid_mask = 0x0; } @@ -1393,7 +1396,7 @@ static ssize_t ctxid_pid_show(struct device *dev, struct etm_drvdata *drvdata = dev_get_drvdata(dev->parent); spin_lock(&drvdata->spinlock); - val = drvdata->ctxid_pid[drvdata->ctxid_idx]; + val = drvdata->ctxid_vpid[drvdata->ctxid_idx]; spin_unlock(&drvdata->spinlock); return sprintf(buf, "%#lx\n", val); @@ -1404,15 +1407,18 @@ static ssize_t ctxid_pid_store(struct device *dev, const char *buf, size_t size) { int ret; - unsigned long val; + unsigned long vpid, pid; struct etm_drvdata *drvdata = dev_get_drvdata(dev->parent); - ret = kstrtoul(buf, 16, &val); + ret = kstrtoul(buf, 16, &vpid); if (ret) return ret; + pid = coresight_vpid_to_pid(vpid); + spin_lock(&drvdata->spinlock); - drvdata->ctxid_pid[drvdata->ctxid_idx] = val; + drvdata->ctxid_pid[drvdata->ctxid_idx] = pid; + drvdata->ctxid_vpid[drvdata->ctxid_idx] = vpid; spin_unlock(&drvdata->spinlock); return size;