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[81.129.173.55]) by smtp.gmail.com with ESMTPSA id qq1sm2359327wjc.0.2015.07.22.06.04.24 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 22 Jul 2015 06:04:24 -0700 (PDT) From: Lee Jones To: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v7 4/5] clk: Provide critical clock support Date: Wed, 22 Jul 2015 14:04:14 +0100 Message-Id: <1437570255-21049-5-git-send-email-lee.jones@linaro.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1437570255-21049-1-git-send-email-lee.jones@linaro.org> References: <1437570255-21049-1-git-send-email-lee.jones@linaro.org> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20150722_060447_801759_BD361E96 X-CRM114-Status: GOOD ( 15.31 ) X-Spam-Score: -2.6 (--) X-Spam-Report: SpamAssassin version 3.4.0 on bombadil.infradead.org summary: Content analysis details: (-2.6 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.7 RCVD_IN_DNSWL_LOW RBL: Sender listed at http://www.dnswl.org/, low trust [209.85.212.181 listed in list.dnswl.org] -0.0 RCVD_IN_MSPIKE_H3 RBL: Good reputation (+3) [209.85.212.181 listed in wl.mailspike.net] -0.0 SPF_PASS SPF: sender matches SPF record -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1% [score: 0.0000] -0.0 RCVD_IN_MSPIKE_WL Mailspike good senders X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: , List-Help: , List-Subscribe: , Cc: devicetree@vger.kernel.org, mturquette@linaro.org, kernel@stlinux.com, s.hauer@pengutronix.de, sboyd@codeaurora.org, geert@linux-m68k.org, maxime.ripard@free-electrons.com, Lee Jones MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patch=linaro.org@lists.infradead.org X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: lee.jones@linaro.org X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.215.47 as permitted sender) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 Lots of platforms contain clocks which if turned off would prove fatal. The only way to recover from these catastrophic failures is to restart the board(s). Now, when a clock provider is registered with the framework it is possible for a list of critical clocks to be supplied which must be kept ungated. Each clock mentioned in the newly introduced 'critical-clock' property will be clk_prepare_enable()d where the normal references will be taken. This will prevent the common clk framework from attempting to gate them during the normal clk_disable_unused() and disable_clock() procedures. Note that it will still be possible for knowledgeable drivers to turn these clocks off using clk_{enable,disable}_critical() calls. Signed-off-by: Lee Jones --- drivers/clk/clk-conf.c | 45 ++++++++++++++++++++++++++++++++++++++++++++- 1 file changed, 44 insertions(+), 1 deletion(-) diff --git a/drivers/clk/clk-conf.c b/drivers/clk/clk-conf.c index aad4796..f83c1c2 100644 --- a/drivers/clk/clk-conf.c +++ b/drivers/clk/clk-conf.c @@ -116,6 +116,45 @@ static int __set_clk_rates(struct device_node *node, bool clk_supplier) return 0; } +static int __set_critical_clocks(struct device_node *node, bool clk_supplier) +{ + struct of_phandle_args clkspec; + struct clk *clk; + struct property *prop; + const __be32 *cur; + uint32_t index; + int ret; + + if (!clk_supplier) + return 0; + + of_property_for_each_u32(node, "critical-clock", prop, cur, index) { + clkspec.np = node; + clkspec.args_count = 1; + clkspec.args[0] = index; + + clk = of_clk_get_from_provider(&clkspec); + if (IS_ERR(clk)) { + pr_err("clk: couldn't get clock %u for %s\n", + index, node->full_name); + return PTR_ERR(clk); + } + + clk_init_critical(clk); + + ret = clk_prepare_enable(clk); + if (ret) { + pr_err("Failed to enable clock %u for %s: %d\n", + index, node->full_name, ret); + return ret; + } + + pr_debug("Setting clock as critical %pC\n", clk); + } + + return 0; +} + /** * of_clk_set_defaults() - parse and set assigned clocks configuration * @node: device node to apply clock settings for @@ -139,6 +178,10 @@ int of_clk_set_defaults(struct device_node *node, bool clk_supplier) if (rc < 0) return rc; - return __set_clk_rates(node, clk_supplier); + rc = __set_clk_rates(node, clk_supplier); + if (rc < 0) + return rc; + + return __set_critical_clocks(node, clk_supplier); } EXPORT_SYMBOL_GPL(of_clk_set_defaults);