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[209.132.180.67]) by mx.google.com with ESMTP id w10si8856410pas.189.2015.07.09.04.51.10; Thu, 09 Jul 2015 04:51:11 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752593AbbGILvJ (ORCPT + 8 others); Thu, 9 Jul 2015 07:51:09 -0400 Received: from mail-pd0-f180.google.com ([209.85.192.180]:32912 "EHLO mail-pd0-f180.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752999AbbGILtu (ORCPT ); Thu, 9 Jul 2015 07:49:50 -0400 Received: by pdbqm3 with SMTP id qm3so20506933pdb.0 for ; Thu, 09 Jul 2015 04:49:49 -0700 (PDT) X-Received: by 10.70.134.133 with SMTP id pk5mr30773926pdb.133.1436442589203; Thu, 09 Jul 2015 04:49:49 -0700 (PDT) Received: from localhost.localdomain ([202.62.77.106]) by smtp.gmail.com with ESMTPSA id qo1sm5709802pbc.89.2015.07.09.04.49.44 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 09 Jul 2015 04:49:48 -0700 (PDT) From: Vaibhav Hiremath To: linux-arm-kernel@lists.infradead.org Cc: robh+dt@kernel.org, sameo@linux.intel.com, lee.jones@linaro.org, k.kozlowski@samsung.com, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Vaibhav Hiremath Subject: [PATCH 4/6] mfd: 88pm800: Enable 32KHZ XO low jitter clock out Date: Thu, 9 Jul 2015 17:17:09 +0530 Message-Id: <1436442431-3471-5-git-send-email-vaibhav.hiremath@linaro.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1436442431-3471-1-git-send-email-vaibhav.hiremath@linaro.org> References: <1436442431-3471-1-git-send-email-vaibhav.hiremath@linaro.org> Sender: devicetree-owner@vger.kernel.org Precedence: list List-ID: X-Mailing-List: devicetree@vger.kernel.org X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: vaibhav.hiremath@linaro.org X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.217.176 as permitted sender) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , 88PM800/860 device supports output of 32KHz low jitter XO clock out on - CLK32K3 - for 88pm800 - CLK32K2 - for 88pm860 Both devices share same register bit-field to configure this. This patch adds support to enable this clock out, using DT property "marvell,88pm800-32khz-xolj-out-en" Since this configuration is controlled through DT property, it is safe to put it as common code. Signed-off-by: Vaibhav Hiremath --- drivers/mfd/88pm800.c | 13 +++++++++++++ include/linux/mfd/88pm80x.h | 1 + 2 files changed, 14 insertions(+) diff --git a/drivers/mfd/88pm800.c b/drivers/mfd/88pm800.c index 80a1bc1..8930fd8 100644 --- a/drivers/mfd/88pm800.c +++ b/drivers/mfd/88pm800.c @@ -526,6 +526,19 @@ static int pm800_init_config(struct pm80x_chip *chip, struct device_node *np) int ret; unsigned int val; + /* Enable 32Khz-out-3 low jitter XO_LJ = 1 in pm800 + * Enable 32Khz-out-2 low jitter XO_LJ = 1 in pm860 + * they are the same bit + */ + if (of_property_read_bool(np, "marvell,88pm800-32khz-xolj-out-en")) { + ret = regmap_update_bits(chip->regmap, + PM800_LOW_POWER2, + PM800_XO_LJ_OUT_EN, + PM800_XO_LJ_OUT_EN); + if (ret) + goto error; + } + switch (chip->type) { case CHIP_PM800: case CHIP_PM805: diff --git a/include/linux/mfd/88pm80x.h b/include/linux/mfd/88pm80x.h index 2ef62af..fb916f1 100644 --- a/include/linux/mfd/88pm80x.h +++ b/include/linux/mfd/88pm80x.h @@ -88,6 +88,7 @@ enum { /* Referance and low power registers */ #define PM800_LOW_POWER1 (0x20) #define PM800_LOW_POWER2 (0x21) +#define PM800_XO_LJ_OUT_EN BIT(5) #define PM800_LOW_POWER_CONFIG3 (0x22) #define PM800_LDOBK_FREEZE BIT(7)