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[209.132.180.67]) by mx.google.com with ESMTP id gt2si33450573pbb.115.2015.07.07.01.44.02; Tue, 07 Jul 2015 01:44:03 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1756717AbbGGIn7 (ORCPT + 29 others); Tue, 7 Jul 2015 04:43:59 -0400 Received: from mail-pa0-f48.google.com ([209.85.220.48]:32996 "EHLO mail-pa0-f48.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1756671AbbGGInd (ORCPT ); Tue, 7 Jul 2015 04:43:33 -0400 Received: by pacws9 with SMTP id ws9so111243922pac.0 for ; Tue, 07 Jul 2015 01:43:32 -0700 (PDT) X-Received: by 10.67.3.193 with SMTP id by1mr6513929pad.21.1436258612369; Tue, 07 Jul 2015 01:43:32 -0700 (PDT) Received: from zcy-ubuntu.spreadtrum.com ([175.111.195.49]) by mx.google.com with ESMTPSA id k3sm21037825pde.18.2015.07.07.01.43.29 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 07 Jul 2015 01:43:31 -0700 (PDT) From: Chunyan Zhang To: mathieu.poirier@linaro.org, gregkh@linuxfoundation.org Cc: broonie@kernel.org, serge.broslavsky@linaro.org, zhang.lyra@gmail.com, linux-arm-kernel@lists.infradead.org, linux-api@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 4/5] coresight-etm3x: Support context-ID tracing when PID namespace is enabled Date: Tue, 7 Jul 2015 16:41:57 +0800 Message-Id: <1436258518-9339-5-git-send-email-zhang.chunyan@linaro.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1436258518-9339-1-git-send-email-zhang.chunyan@linaro.org> References: <1436258518-9339-1-git-send-email-zhang.chunyan@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: list List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: zhang.chunyan@linaro.org X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.215.48 as permitted sender) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , The Coresight ETM drivers already support context-ID tracing, but it won't work when PID namespace is enabled. This is because when using PID namespace a process id (ie. VPID) seen from the current namespace differs from the id (ie. PID) seen by kernel. So when users write the process id seen by themselves to ETM, there needs to be a translation from VPID to PID, as such ETM drivers will write the PID into the Context ID register correctly. Signed-off-by: Chunyan Zhang --- drivers/hwtracing/coresight/coresight-etm.h | 3 +++ drivers/hwtracing/coresight/coresight-etm3x.c | 16 +++++++++++----- 2 files changed, 14 insertions(+), 5 deletions(-) diff --git a/drivers/hwtracing/coresight/coresight-etm.h b/drivers/hwtracing/coresight/coresight-etm.h index 52af5f0..b4481eb 100644 --- a/drivers/hwtracing/coresight/coresight-etm.h +++ b/drivers/hwtracing/coresight/coresight-etm.h @@ -184,6 +184,8 @@ * @seq_curr_state: current value of the sequencer register. * @ctxid_idx: index for the context ID registers. * @ctxid_pid: value for the context ID to trigger on. + * @ctxid_vpid: Virtual PID seen by users if PID namespace is enabled, otherwise + * the same value of ctxid_pid. * @ctxid_mask: mask applicable to all the context IDs. * @sync_freq: Synchronisation frequency. * @timestamp_event: Defines an event that requests the insertion @@ -236,6 +238,7 @@ struct etm_drvdata { u32 seq_curr_state; u8 ctxid_idx; u32 ctxid_pid[ETM_MAX_CTXID_CMP]; + u32 ctxid_vpid[ETM_MAX_CTXID_CMP]; u32 ctxid_mask; u32 sync_freq; u32 timestamp_event; diff --git a/drivers/hwtracing/coresight/coresight-etm3x.c b/drivers/hwtracing/coresight/coresight-etm3x.c index cfda302..996f083 100644 --- a/drivers/hwtracing/coresight/coresight-etm3x.c +++ b/drivers/hwtracing/coresight/coresight-etm3x.c @@ -237,8 +237,11 @@ static void etm_set_default(struct etm_drvdata *drvdata) drvdata->seq_curr_state = 0x0; drvdata->ctxid_idx = 0x0; - for (i = 0; i < drvdata->nr_ctxid_cmp; i++) + for (i = 0; i < drvdata->nr_ctxid_cmp; i++) { drvdata->ctxid_pid[i] = 0x0; + drvdata->ctxid_vpid[i] = 0x0; + } + drvdata->ctxid_mask = 0x0; } @@ -1393,7 +1396,7 @@ static ssize_t ctxid_pid_show(struct device *dev, struct etm_drvdata *drvdata = dev_get_drvdata(dev->parent); spin_lock(&drvdata->spinlock); - val = drvdata->ctxid_pid[drvdata->ctxid_idx]; + val = drvdata->ctxid_vpid[drvdata->ctxid_idx]; spin_unlock(&drvdata->spinlock); return sprintf(buf, "%#lx\n", val); @@ -1404,15 +1407,18 @@ static ssize_t ctxid_pid_store(struct device *dev, const char *buf, size_t size) { int ret; - unsigned long val; + unsigned long vpid, pid; struct etm_drvdata *drvdata = dev_get_drvdata(dev->parent); - ret = kstrtoul(buf, 16, &val); + ret = kstrtoul(buf, 16, &vpid); if (ret) return ret; + pid = coresight_vpid_to_pid(vpid); + spin_lock(&drvdata->spinlock); - drvdata->ctxid_pid[drvdata->ctxid_idx] = val; + drvdata->ctxid_pid[drvdata->ctxid_idx] = pid; + drvdata->ctxid_vpid[drvdata->ctxid_idx] = vpid; spin_unlock(&drvdata->spinlock); return size;