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[2001:1868:205::9]) by mx.google.com with ESMTPS id e3si26391496pdj.210.2015.07.05.19.21.48 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sun, 05 Jul 2015 19:21:49 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-arm-kernel-bounces+patch=linaro.org@lists.infradead.org designates 2001:1868:205::9 as permitted sender) client-ip=2001:1868:205::9; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1ZBw1Q-000199-UD; Mon, 06 Jul 2015 02:20:40 +0000 Received: from mail-pd0-f174.google.com ([209.85.192.174]) by bombadil.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1ZBw0F-0006JI-H1 for linux-arm-kernel@lists.infradead.org; Mon, 06 Jul 2015 02:19:28 +0000 Received: by pdbdz6 with SMTP id dz6so1066497pdb.0 for ; Sun, 05 Jul 2015 19:19:07 -0700 (PDT) X-Received: by 10.70.96.2 with SMTP id do2mr25234433pdb.67.1436149147184; Sun, 05 Jul 2015 19:19:07 -0700 (PDT) Received: from localhost ([120.136.34.248]) by mx.google.com with ESMTPSA id oo3sm16284656pac.31.2015.07.05.19.19.05 (version=TLSv1 cipher=RC4-SHA bits=128/128); Sun, 05 Jul 2015 19:19:06 -0700 (PDT) From: shannon.zhao@linaro.org To: kvmarm@lists.cs.columbia.edu Subject: [PATCH 15/18] KVM: ARM64: Add reset and access handlers for PMSWINC_EL0 register Date: Mon, 6 Jul 2015 10:17:45 +0800 Message-Id: <1436149068-3784-16-git-send-email-shannon.zhao@linaro.org> X-Mailer: git-send-email 1.9.5.msysgit.1 In-Reply-To: <1436149068-3784-1-git-send-email-shannon.zhao@linaro.org> References: <1436149068-3784-1-git-send-email-shannon.zhao@linaro.org> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20150705_191927_593731_97F497CF X-CRM114-Status: GOOD ( 16.25 ) X-Spam-Score: -2.6 (--) X-Spam-Report: SpamAssassin version 3.4.0 on bombadil.infradead.org summary: Content analysis details: (-2.6 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 RCVD_IN_MSPIKE_H2 RBL: Average reputation (+2) [209.85.192.174 listed in wl.mailspike.net] -0.7 RCVD_IN_DNSWL_LOW RBL: Sender listed at http://www.dnswl.org/, low trust [209.85.192.174 listed in list.dnswl.org] -0.0 SPF_PASS SPF: sender matches SPF record -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1% [score: 0.0000] X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: , List-Help: , List-Subscribe: , Cc: kvm@vger.kernel.org, marc.zyngier@arm.com, will.deacon@arm.com, linux-arm-kernel@lists.infradead.org, zhaoshenglong@huawei.com, alex.bennee@linaro.org, christoffer.dall@linaro.org, shannon.zhao@linaro.org MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patch=linaro.org@lists.infradead.org X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: shannon.zhao@linaro.org X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.215.46 as permitted sender) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 From: Shannon Zhao Add access handler which emulates writing and reading PMSWINC_EL0 register and add support for creating software increment event. Signed-off-by: Shannon Zhao --- arch/arm64/kvm/sys_regs.c | 15 ++++++++++++++- include/kvm/arm_pmu.h | 2 ++ virt/kvm/arm/pmu.c | 20 ++++++++++++++++++++ 3 files changed, 36 insertions(+), 1 deletion(-) diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c index d5984d0..70afcba 100644 --- a/arch/arm64/kvm/sys_regs.c +++ b/arch/arm64/kvm/sys_regs.c @@ -535,6 +535,19 @@ static bool access_pmuserenr(struct kvm_vcpu *vcpu, return true; } +/* PMSWINC_EL0 accessor. */ +static bool access_pmswinc(struct kvm_vcpu *vcpu, + const struct sys_reg_params *p, + const struct sys_reg_desc *r) +{ + if (p->is_write) + kvm_pmu_software_increment(vcpu, *vcpu_reg(vcpu, p->Rt)); + else + return read_zero(vcpu, p); + + return true; +} + /* Silly macro to expand the DBG{BCR,BVR,WVR,WCR}n_EL1 registers in one go */ #define DBG_BCR_BVR_WCR_WVR_EL1(n) \ /* DBGBVRn_EL1 */ \ @@ -738,7 +751,7 @@ static const struct sys_reg_desc sys_reg_descs[] = { access_pmovsclr, reset_unknown, PMOVSCLR_EL0 }, /* PMSWINC_EL0 */ { Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1100), Op2(0b100), - trap_raz_wi }, + access_pmswinc, reset_unknown, PMSWINC_EL0 }, /* PMSELR_EL0 */ { Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1100), Op2(0b101), access_pmselr, reset_unknown, PMSELR_EL0 }, diff --git a/include/kvm/arm_pmu.h b/include/kvm/arm_pmu.h index 4f3d8a6..6985809 100644 --- a/include/kvm/arm_pmu.h +++ b/include/kvm/arm_pmu.h @@ -54,6 +54,7 @@ void kvm_pmu_disable_counter(struct kvm_vcpu *vcpu, unsigned long val); void kvm_pmu_enable_counter(struct kvm_vcpu *vcpu, unsigned long val); void kvm_pmu_disable_interrupt(struct kvm_vcpu *vcpu, unsigned long val); void kvm_pmu_enable_interrupt(struct kvm_vcpu *vcpu, unsigned long val); +void kvm_pmu_software_increment(struct kvm_vcpu *vcpu, unsigned long val); void kvm_pmu_set_counter_event_type(struct kvm_vcpu *vcpu, unsigned long data, unsigned long select_idx); void kvm_pmu_init(struct kvm_vcpu *vcpu); @@ -70,6 +71,7 @@ void kvm_pmu_disable_counter(struct kvm_vcpu *vcpu, unsigned long val) {} void kvm_pmu_enable_counter(struct kvm_vcpu *vcpu, unsigned long val) {} void kvm_pmu_disable_interrupt(struct kvm_vcpu *vcpu, unsigned long val) {} void kvm_pmu_enable_interrupt(struct kvm_vcpu *vcpu, unsigned long val) {} +void kvm_pmu_software_increment(struct kvm_vcpu *vcpu, unsigned long val) {} void kvm_pmu_set_counter_event_type(struct kvm_vcpu *vcpu, unsigned long data, unsigned long select_idx) {} static inline void kvm_pmu_init(struct kvm_vcpu *vcpu) {} diff --git a/virt/kvm/arm/pmu.c b/virt/kvm/arm/pmu.c index 7023ad5..e655426 100644 --- a/virt/kvm/arm/pmu.c +++ b/virt/kvm/arm/pmu.c @@ -203,6 +203,22 @@ void kvm_pmu_disable_interrupt(struct kvm_vcpu *vcpu, unsigned long val) } /** + * kvm_pmu_software_increment - do software increment + * @vcpu: The vcpu pointer + * @val: the value guest writes to PMSWINC_EL0 register + */ +void kvm_pmu_software_increment(struct kvm_vcpu *vcpu, unsigned long val) +{ + int select_idx = find_first_bit(&val, 31); + struct kvm_pmu *pmu = &vcpu->arch.pmu; + struct kvm_pmc *pmc = &pmu->pmc[select_idx]; + + if (pmu->user_enable & 0x3) + if ((pmc->eventsel == 0) && (pmc->enable == true)) + pmc->counter++; +} + +/** * kvm_pmu_find_hw_event - find hardware event * @pmu: The pmu pointer * @event_select: The number of selected event type @@ -280,6 +296,10 @@ void kvm_pmu_set_counter_event_type(struct kvm_vcpu *vcpu, unsigned long data, kvm_pmu_stop_counter(vcpu, select_idx); pmc->eventsel = data & ARMV8_EVTYPE_EVENT; + /* For software increment event we don't need to create perf event */ + if (pmc->eventsel == 0) + return; + config = kvm_pmu_find_hw_event(pmu, pmc->eventsel); if (config != PERF_COUNT_HW_MAX) { type = PERF_TYPE_HARDWARE;