From patchwork Mon Jul 6 02:17:39 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Shannon Zhao X-Patchwork-Id: 50681 Return-Path: X-Original-To: linaro@patches.linaro.org Delivered-To: linaro@patches.linaro.org Received: from mail-wi0-f198.google.com (mail-wi0-f198.google.com [209.85.212.198]) by ip-10-151-82-157.ec2.internal (Postfix) with ESMTPS id 0431E22A07 for ; Mon, 6 Jul 2015 02:20:42 +0000 (UTC) Received: by wipp2 with SMTP id p2sf26876523wip.2 for ; Sun, 05 Jul 2015 19:20:41 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:delivered-to:from:to:subject:date:message-id :in-reply-to:references:precedence:list-id:list-unsubscribe :list-archive:list-post:list-help:list-subscribe:cc:mime-version :content-type:content-transfer-encoding:sender:errors-to :x-original-sender:x-original-authentication-results:mailing-list; bh=EZxDIyxTTnXuvwADczsoFww7KuCkczWqLYWJ7c4c8x4=; b=aXbJD1aYlTLxiLh6f8vlf+tvkK51Qj+NvLBRCS5Q5tcmNoMva/TY/bIvdtrsBRsQaC n7MXrvCM9iioxkcHlzt2kfJlu4wmY+mQhj4D6HUaFLwBzqCFEWzB/NrHx5++vuQ3PLA1 WLpDI4X0SvA7Kf26+O562uBPZegmRaoF3VNrrdzTPwFvpzU8m3sEOABfYPQ/hYcb+jGM SBAu733gX3BcgWmWCFUfh5u6rWXzLy5hslMJJBfvP05+PBUIhU4gaqWkBdyqNHOt2TKb jxR0d4sthDB9VnVX01VM7sAd6iwCpbIv0FSZjNQ6DFfMBVqLgfdUw26tltP+39JOdVEL DXdQ== X-Gm-Message-State: ALoCoQnMm6oRm1ha/QlntsuqnMzsz+x+tPDby9rJT7YhlqIeR/VG0ZFAvqn8nWi3PrvOVWL1scv6 X-Received: by 10.112.42.236 with SMTP id r12mr29527832lbl.2.1436149241276; Sun, 05 Jul 2015 19:20:41 -0700 (PDT) X-BeenThere: patchwork-forward@linaro.org Received: by 10.152.30.103 with SMTP id r7ls532994lah.106.gmail; Sun, 05 Jul 2015 19:20:41 -0700 (PDT) X-Received: by 10.112.142.232 with SMTP id rz8mr45320528lbb.74.1436149241130; Sun, 05 Jul 2015 19:20:41 -0700 (PDT) Received: from mail-la0-f47.google.com (mail-la0-f47.google.com. [209.85.215.47]) by mx.google.com with ESMTPS id f9si13951344laa.60.2015.07.05.19.20.41 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sun, 05 Jul 2015 19:20:41 -0700 (PDT) Received-SPF: pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.215.47 as permitted sender) client-ip=209.85.215.47; Received: by laar3 with SMTP id r3so137697284laa.0 for ; Sun, 05 Jul 2015 19:20:41 -0700 (PDT) X-Received: by 10.112.234.200 with SMTP id ug8mr46318667lbc.117.1436149241041; Sun, 05 Jul 2015 19:20:41 -0700 (PDT) X-Forwarded-To: patchwork-forward@linaro.org X-Forwarded-For: patch@linaro.org patchwork-forward@linaro.org Delivered-To: patch@linaro.org Received: by 10.112.108.230 with SMTP id hn6csp1426209lbb; Sun, 5 Jul 2015 19:20:39 -0700 (PDT) X-Received: by 10.66.159.34 with SMTP id wz2mr98004515pab.58.1436149239041; Sun, 05 Jul 2015 19:20:39 -0700 (PDT) Received: from bombadil.infradead.org (bombadil.infradead.org. [2001:1868:205::9]) by mx.google.com with ESMTPS id l3si26420440pdp.109.2015.07.05.19.20.38 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sun, 05 Jul 2015 19:20:39 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-arm-kernel-bounces+patch=linaro.org@lists.infradead.org designates 2001:1868:205::9 as permitted sender) client-ip=2001:1868:205::9; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1ZBw0G-0006gS-Mp; Mon, 06 Jul 2015 02:19:28 +0000 Received: from mail-pa0-f50.google.com ([209.85.220.50]) by bombadil.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1ZBvzl-0005wD-Pd for linux-arm-kernel@lists.infradead.org; Mon, 06 Jul 2015 02:18:58 +0000 Received: by pacgz10 with SMTP id gz10so13152785pac.3 for ; Sun, 05 Jul 2015 19:18:39 -0700 (PDT) X-Received: by 10.70.130.79 with SMTP id oc15mr18281287pdb.55.1436149119195; Sun, 05 Jul 2015 19:18:39 -0700 (PDT) Received: from localhost ([120.136.34.248]) by mx.google.com with ESMTPSA id hl6sm9582209pdb.28.2015.07.05.19.18.37 (version=TLSv1 cipher=RC4-SHA bits=128/128); Sun, 05 Jul 2015 19:18:38 -0700 (PDT) From: shannon.zhao@linaro.org To: kvmarm@lists.cs.columbia.edu Subject: [PATCH 09/18] KVM: ARM64: Add reset and access handlers for PMXEVCNTR_EL0 register Date: Mon, 6 Jul 2015 10:17:39 +0800 Message-Id: <1436149068-3784-10-git-send-email-shannon.zhao@linaro.org> X-Mailer: git-send-email 1.9.5.msysgit.1 In-Reply-To: <1436149068-3784-1-git-send-email-shannon.zhao@linaro.org> References: <1436149068-3784-1-git-send-email-shannon.zhao@linaro.org> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20150705_191857_887392_255517FC X-CRM114-Status: GOOD ( 15.65 ) X-Spam-Score: -2.6 (--) X-Spam-Report: SpamAssassin version 3.4.0 on bombadil.infradead.org summary: Content analysis details: (-2.6 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 RCVD_IN_MSPIKE_H3 RBL: Good reputation (+3) [209.85.220.50 listed in wl.mailspike.net] -0.7 RCVD_IN_DNSWL_LOW RBL: Sender listed at http://www.dnswl.org/, low trust [209.85.220.50 listed in list.dnswl.org] -0.0 SPF_PASS SPF: sender matches SPF record -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1% [score: 0.0000] -0.0 RCVD_IN_MSPIKE_WL Mailspike good senders X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: , List-Help: , List-Subscribe: , Cc: kvm@vger.kernel.org, marc.zyngier@arm.com, will.deacon@arm.com, linux-arm-kernel@lists.infradead.org, zhaoshenglong@huawei.com, alex.bennee@linaro.org, christoffer.dall@linaro.org, shannon.zhao@linaro.org MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patch=linaro.org@lists.infradead.org X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: shannon.zhao@linaro.org X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.215.47 as permitted sender) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 From: Shannon Zhao Since the reset value of PMXEVTYPER_EL0 is UNKNOWN, use reset_unknown for its reset handler. Add access handler which emulates writing and reading PMXEVTYPER_EL0 register. When reading PMXEVCNTR_EL0, call perf_event_read_value to get the count value of the perf event. Signed-off-by: Shannon Zhao --- arch/arm64/kvm/sys_regs.c | 21 ++++++++++++++++++++- include/kvm/arm_pmu.h | 11 +++++++++++ virt/kvm/arm/pmu.c | 37 +++++++++++++++++++++++++++++++++++++ 3 files changed, 68 insertions(+), 1 deletion(-) diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c index b4f8dd9..2bcf1a0 100644 --- a/arch/arm64/kvm/sys_regs.c +++ b/arch/arm64/kvm/sys_regs.c @@ -356,6 +356,25 @@ static bool access_pmxevtyper(struct kvm_vcpu *vcpu, return true; } +static bool access_pmxevcntr(struct kvm_vcpu *vcpu, + const struct sys_reg_params *p, + const struct sys_reg_desc *r) +{ + unsigned long val; + + if (p->is_write) { + val = *vcpu_reg(vcpu, p->Rt); + kvm_pmu_set_counter_value(vcpu, vcpu_sys_reg(vcpu, PMSELR_EL0), + val & 0xffffffffUL); + } else { + val = kvm_pmu_get_counter_value(vcpu, + vcpu_sys_reg(vcpu, PMSELR_EL0)); + *vcpu_reg(vcpu, p->Rt) = val; + } + + return true; +} + /* Silly macro to expand the DBG{BCR,BVR,WVR,WCR}n_EL1 registers in one go */ #define DBG_BCR_BVR_WCR_WVR_EL1(n) \ /* DBGBVRn_EL1 */ \ @@ -577,7 +596,7 @@ static const struct sys_reg_desc sys_reg_descs[] = { access_pmxevtyper, reset_unknown, PMXEVTYPER_EL0 }, /* PMXEVCNTR_EL0 */ { Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1101), Op2(0b010), - trap_raz_wi }, + access_pmxevcntr, reset_unknown, PMXEVCNTR_EL0 }, /* PMUSERENR_EL0 */ { Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1110), Op2(0b000), trap_raz_wi }, diff --git a/include/kvm/arm_pmu.h b/include/kvm/arm_pmu.h index 1050b24..40ab4a0 100644 --- a/include/kvm/arm_pmu.h +++ b/include/kvm/arm_pmu.h @@ -45,11 +45,22 @@ struct kvm_pmu { #ifdef CONFIG_KVM_ARM_PMU void kvm_pmu_vcpu_reset(struct kvm_vcpu *vcpu); +void kvm_pmu_set_counter_value(struct kvm_vcpu *vcpu, unsigned long select_idx, + unsigned long val); +unsigned long kvm_pmu_get_counter_value(struct kvm_vcpu *vcpu, + unsigned long select_idx); void kvm_pmu_set_counter_event_type(struct kvm_vcpu *vcpu, unsigned long data, unsigned long select_idx); void kvm_pmu_init(struct kvm_vcpu *vcpu); #else static inline void kvm_pmu_vcpu_reset(struct kvm_vcpu *vcpu) {} +void kvm_pmu_set_counter_value(struct kvm_vcpu *vcpu, unsigned long select_idx, + unsigned long val) {} +unsigned long kvm_pmu_get_counter_value(struct kvm_vcpu *vcpu, + unsigned long select_idx) +{ + return 0; +} void kvm_pmu_set_counter_event_type(struct kvm_vcpu *vcpu, unsigned long data, unsigned long select_idx) {} static inline void kvm_pmu_init(struct kvm_vcpu *vcpu) {} diff --git a/virt/kvm/arm/pmu.c b/virt/kvm/arm/pmu.c index 50a3c82..361fa51 100644 --- a/virt/kvm/arm/pmu.c +++ b/virt/kvm/arm/pmu.c @@ -97,6 +97,43 @@ void kvm_pmu_vcpu_reset(struct kvm_vcpu *vcpu) } /** + * kvm_pmu_set_counter_value - set PMU counter value + * @vcpu: The vcpu pointer + * @select_idx: The counter index + * @val: the value to be set + */ +void kvm_pmu_set_counter_value(struct kvm_vcpu *vcpu, unsigned long select_idx, + unsigned long val) +{ + struct kvm_pmu *pmu = &vcpu->arch.pmu; + struct kvm_pmc *pmc = &pmu->pmc[select_idx]; + + pmc->counter = val; +} + +/** + * kvm_pmu_set_counter_value - set PMU counter value + * @vcpu: The vcpu pointer + * @select_idx: The counter index + * + * Call perf_event API to get the event count + */ +unsigned long kvm_pmu_get_counter_value(struct kvm_vcpu *vcpu, + unsigned long select_idx) +{ + u64 enabled, running; + struct kvm_pmu *pmu = &vcpu->arch.pmu; + struct kvm_pmc *pmc = &pmu->pmc[select_idx]; + unsigned long counter = pmc->counter; + + if (pmc->perf_event) { + counter += perf_event_read_value(pmc->perf_event, + &enabled, &running); + } + return counter; +} + +/** * kvm_pmu_find_hw_event - find hardware event * @pmu: The pmu pointer * @event_select: The number of selected event type