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[209.85.217.178]) by mx.google.com with ESMTPS id e14si23992161lbo.160.2015.06.25.00.32.19 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 25 Jun 2015 00:32:19 -0700 (PDT) Received-SPF: pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.217.178 as permitted sender) client-ip=209.85.217.178; Received: by lbbwc1 with SMTP id wc1so39975169lbb.2 for ; Thu, 25 Jun 2015 00:32:19 -0700 (PDT) X-Received: by 10.152.4.163 with SMTP id l3mr10926758lal.35.1435217539393; Thu, 25 Jun 2015 00:32:19 -0700 (PDT) X-Forwarded-To: patchwork-forward@linaro.org X-Forwarded-For: patch@linaro.org patchwork-forward@linaro.org Delivered-To: patch@linaro.org Received: by 10.112.108.230 with SMTP id hn6csp405137lbb; Thu, 25 Jun 2015 00:32:18 -0700 (PDT) X-Received: by 10.70.87.195 with SMTP id ba3mr88991257pdb.154.1435217537627; Thu, 25 Jun 2015 00:32:17 -0700 (PDT) Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id v16si43635925pbs.166.2015.06.25.00.32.16; Thu, 25 Jun 2015 00:32:17 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752076AbbFYHcL (ORCPT + 30 others); Thu, 25 Jun 2015 03:32:11 -0400 Received: from mail-pd0-f174.google.com ([209.85.192.174]:35959 "EHLO mail-pd0-f174.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751728AbbFYHb6 (ORCPT ); Thu, 25 Jun 2015 03:31:58 -0400 Received: by pdcu2 with SMTP id u2so47832911pdc.3 for ; Thu, 25 Jun 2015 00:31:58 -0700 (PDT) X-Received: by 10.70.51.67 with SMTP id i3mr88367207pdo.145.1435217518304; Thu, 25 Jun 2015 00:31:58 -0700 (PDT) Received: from localhost.localdomain ([202.62.77.106]) by mx.google.com with ESMTPSA id nl10sm29020111pdb.38.2015.06.25.00.31.54 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 25 Jun 2015 00:31:57 -0700 (PDT) From: Vaibhav Hiremath To: linux-arm-kernel@lists.infradead.org Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, lee.jones@linaro.org, robh+dt@kernel.org, yizhang@marvell.com, Vaibhav Hiremath , Zhao Ye Subject: [PATCH-v4 2/3] mfd: 88pm800: Set default interrupt clear method Date: Thu, 25 Jun 2015 12:56:28 +0530 Message-Id: <1435217189-19578-3-git-send-email-vaibhav.hiremath@linaro.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1435217189-19578-1-git-send-email-vaibhav.hiremath@linaro.org> References: <1435217189-19578-1-git-send-email-vaibhav.hiremath@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: list List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: vaibhav.hiremath@linaro.org X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.217.178 as permitted sender) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , As per the spec, bit 1 (INT_CLEAR_MODE) of reg addr 0xe (page 0) controls the method of clearing interrupt status of 88pm800 family of devices; 0: clear on read 1: clear on write If pdata is not coming from board file, then set the default irq clear method to "irq clear on write" Also, as suggested by "Lee Jones" renaming variable field to appropriate name. Signed-off-by: Zhao Ye Signed-off-by: Vaibhav Hiremath --- drivers/mfd/88pm800.c | 15 ++++++++++----- include/linux/mfd/88pm80x.h | 6 ++++-- 2 files changed, 14 insertions(+), 7 deletions(-) diff --git a/drivers/mfd/88pm800.c b/drivers/mfd/88pm800.c index 40fd014..e0cd7ad 100644 --- a/drivers/mfd/88pm800.c +++ b/drivers/mfd/88pm800.c @@ -376,7 +376,7 @@ static int device_irq_init_800(struct pm80x_chip *chip) { struct regmap *map = chip->regmap; unsigned long flags = IRQF_ONESHOT; - int data, mask, ret = -EINVAL; + int irq_clr_mode, mask, ret = -EINVAL; if (!map || !chip->irq) { dev_err(chip->dev, "incorrect parameters\n"); @@ -384,15 +384,16 @@ static int device_irq_init_800(struct pm80x_chip *chip) } /* - * irq_mode defines the way of clearing interrupt. it's read-clear by - * default. + * irq_clr_on_wr defines the way of clearing interrupt by + * read/write(0/1). It's read-clear by default. */ mask = PM800_WAKEUP2_INV_INT | PM800_WAKEUP2_INT_CLEAR | PM800_WAKEUP2_INT_MASK; - data = PM800_WAKEUP2_INT_CLEAR; - ret = regmap_update_bits(map, PM800_WAKEUP2, mask, data); + irq_clr_mode = (chip->irq_clr_on_wr) ? + PM800_WAKEUP2_INT_WRITE_CLEAR : PM800_WAKEUP2_INT_READ_CLEAR; + ret = regmap_update_bits(map, PM800_WAKEUP2, mask, irq_clr_mode); if (ret < 0) goto out; @@ -514,6 +515,7 @@ static int device_800_init(struct pm80x_chip *chip, } chip->regmap_irq_chip = &pm800_irq_chip; + chip->irq_clr_on_wr = pdata->irq_clr_on_wr; ret = device_irq_init_800(chip); if (ret < 0) { @@ -566,6 +568,9 @@ static int pm800_probe(struct i2c_client *client, pdata = devm_kzalloc(&client->dev, sizeof(*pdata), GFP_KERNEL); if (!pdata) return -ENOMEM; + + /* by default, set irq clear method on write */ + pdata->irq_clr_on_wr = true; } ret = pm80x_init(client); diff --git a/include/linux/mfd/88pm80x.h b/include/linux/mfd/88pm80x.h index 97cb283..94b3dcd 100644 --- a/include/linux/mfd/88pm80x.h +++ b/include/linux/mfd/88pm80x.h @@ -77,6 +77,8 @@ enum { #define PM800_WAKEUP2 (0x0E) #define PM800_WAKEUP2_INV_INT (1 << 0) #define PM800_WAKEUP2_INT_CLEAR (1 << 1) +#define PM800_WAKEUP2_INT_READ_CLEAR (0 << 1) +#define PM800_WAKEUP2_INT_WRITE_CLEAR (1 << 1) #define PM800_WAKEUP2_INT_MASK (1 << 2) #define PM800_POWER_UP_LOG (0x10) @@ -300,7 +302,7 @@ struct pm80x_chip { struct regmap_irq_chip_data *irq_data; int type; int irq; - int irq_mode; + int irq_clr_on_wr; /* '1': Clear on write, '0': Clear on read*/ unsigned long wu_flag; spinlock_t lock; }; @@ -315,7 +317,7 @@ struct pm80x_platform_data { */ struct regulator_init_data *regulators[PM800_ID_RG_MAX]; unsigned int num_regulators; - int irq_mode; /* Clear interrupt by read/write(0/1) */ + int irq_clr_on_wr; /* Clear interrupt by read/write(0/1) */ int batt_det; /* enable/disable */ int (*plat_config)(struct pm80x_chip *chip, struct pm80x_platform_data *pdata);