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[2001:1868:205::9]) by mx.google.com with ESMTPS id a10si22876672pas.176.2015.06.22.03.45.59 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 22 Jun 2015 03:46:02 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-arm-kernel-bounces+patch=linaro.org@lists.infradead.org designates 2001:1868:205::9 as permitted sender) client-ip=2001:1868:205::9; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1Z6zD8-0006yy-70; Mon, 22 Jun 2015 10:44:18 +0000 Received: from mail-pd0-f175.google.com ([209.85.192.175]) by bombadil.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1Z6zBS-0005uT-3H for linux-arm-kernel@lists.infradead.org; Mon, 22 Jun 2015 10:42:34 +0000 Received: by pdjn11 with SMTP id n11so136460878pdj.0 for ; Mon, 22 Jun 2015 03:42:18 -0700 (PDT) X-Received: by 10.68.69.37 with SMTP id b5mr58206631pbu.35.1434969738061; Mon, 22 Jun 2015 03:42:18 -0700 (PDT) Received: from localhost ([104.207.83.42]) by mx.google.com with ESMTPSA id dd3sm19611737pad.45.2015.06.22.03.42.16 (version=TLSv1 cipher=RC4-SHA bits=128/128); Mon, 22 Jun 2015 03:42:16 -0700 (PDT) From: Zhichao Huang To: kvm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, kvmarm@lists.cs.columbia.edu, christoffer.dall@linaro.org, marc.zyngier@arm.com, alex.bennee@linaro.org, will.deacon@arm.com Subject: [PATCH v3 07/11] KVM: arm: add trap handlers for 64-bit debug registers Date: Mon, 22 Jun 2015 18:41:30 +0800 Message-Id: <1434969694-7432-8-git-send-email-zhichao.huang@linaro.org> X-Mailer: git-send-email 1.9.5.msysgit.1 In-Reply-To: <1434969694-7432-1-git-send-email-zhichao.huang@linaro.org> References: <1434969694-7432-1-git-send-email-zhichao.huang@linaro.org> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20150622_034234_192067_8F9DD678 X-CRM114-Status: GOOD ( 10.37 ) X-Spam-Score: -0.7 (/) X-Spam-Report: SpamAssassin version 3.4.0 on bombadil.infradead.org summary: Content analysis details: (-0.7 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.7 RCVD_IN_DNSWL_LOW RBL: Sender listed at http://www.dnswl.org/, low trust [209.85.192.175 listed in list.dnswl.org] -0.0 RCVD_IN_MSPIKE_H2 RBL: Average reputation (+2) [209.85.192.175 listed in wl.mailspike.net] -0.0 SPF_PASS SPF: sender matches SPF record Cc: huangzhichao@huawei.com, Zhichao Huang X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.18-1 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: , List-Help: , List-Subscribe: , MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patch=linaro.org@lists.infradead.org X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: zhichao.huang@linaro.org X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.215.44 as permitted sender) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 Add handlers for all the 64-bit debug registers. There is an overlap between 32 and 64bit registers. Make sure that 64-bit registers preceding 32-bit ones. Signed-off-by: Zhichao Huang Reviewed-by: Christoffer Dall --- arch/arm/kvm/coproc.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/arm/kvm/coproc.c b/arch/arm/kvm/coproc.c index 59b65b7..eeee648 100644 --- a/arch/arm/kvm/coproc.c +++ b/arch/arm/kvm/coproc.c @@ -435,9 +435,17 @@ static const struct coproc_reg cp15_regs[] = { { CRn( 1), CRm((n)), Op1( 0), Op2( 1), is32, trap_raz_wi } /* + * Architected CP14 registers. + * * Trapped cp14 registers. We generally ignore most of the external * debug, on the principle that they don't really make sense to a * guest. Revisit this one day, whould this principle change. + * + * CRn denotes the primary register number, but is copied to the CRm in the + * user space API for 64-bit register access in line with the terminology used + * in the ARM ARM. + * Important: Must be sorted ascending by CRn, CRM, Op1, Op2 and with 64-bit + * registers preceding 32-bit ones. */ static const struct coproc_reg cp14_regs[] = { /* DBGIDR */ @@ -445,10 +453,14 @@ static const struct coproc_reg cp14_regs[] = { /* DBGDTRRXext */ { CRn( 0), CRm( 0), Op1( 0), Op2( 2), is32, trap_raz_wi }, DBG_BCR_BVR_WCR_WVR(0), + /* DBGDRAR (64bit) */ + { CRn( 0), CRm( 1), Op1( 0), Op2( 0), is64, trap_raz_wi}, /* DBGDSCRint */ { CRn( 0), CRm( 1), Op1( 0), Op2( 0), is32, trap_dbgdscr, NULL, cp14_DBGDSCRext }, DBG_BCR_BVR_WCR_WVR(1), + /* DBGDSAR (64bit) */ + { CRn( 0), CRm( 2), Op1( 0), Op2( 0), is64, trap_raz_wi}, /* DBGDSCRext */ { CRn( 0), CRm( 2), Op1( 0), Op2( 2), is32, trap_debug32, reset_val, cp14_DBGDSCRext, 0 },