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[209.132.180.67]) by mx.google.com with ESMTP id rx6si7548929pab.219.2015.06.17.12.02.00; Wed, 17 Jun 2015 12:02:01 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753760AbbFQTB7 (ORCPT + 7 others); Wed, 17 Jun 2015 15:01:59 -0400 Received: from mail-pa0-f54.google.com ([209.85.220.54]:35246 "EHLO mail-pa0-f54.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1757670AbbFQTBP (ORCPT ); Wed, 17 Jun 2015 15:01:15 -0400 Received: by pacyx8 with SMTP id yx8so42432231pac.2 for ; Wed, 17 Jun 2015 12:01:14 -0700 (PDT) X-Received: by 10.70.90.232 with SMTP id bz8mr1261220pdb.120.1434567673920; Wed, 17 Jun 2015 12:01:13 -0700 (PDT) Received: from localhost.localdomain ([202.62.77.106]) by mx.google.com with ESMTPSA id y1sm5521122pdy.2.2015.06.17.12.01.09 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 17 Jun 2015 12:01:12 -0700 (PDT) From: Vaibhav Hiremath To: linux-arm-kernel@lists.infradead.org Cc: robh+dt@kernel.org, lee.jones@linaro.org, devicetree@vger.kernel.org, rtc-linux@googlegroups.com, linux-kernel@vger.kernel.org, Vaibhav Hiremath , Zhao Ye Subject: [PATCH-v2 2/3] mfd: 88pm800: Allow configuration of interrupt clear method Date: Thu, 18 Jun 2015 00:28:07 +0530 Message-Id: <1434567488-6477-4-git-send-email-vaibhav.hiremath@linaro.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1434567488-6477-1-git-send-email-vaibhav.hiremath@linaro.org> References: <1434567488-6477-1-git-send-email-vaibhav.hiremath@linaro.org> Sender: devicetree-owner@vger.kernel.org Precedence: list List-ID: X-Mailing-List: devicetree@vger.kernel.org X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: vaibhav.hiremath@linaro.org X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.215.42 as permitted sender) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , As per the spec, bit 1 (INT_CLEAR_MODE) of reg addr 0xe (page 0) controls the method of clearing interrupt status of 88pm800 family of devices; 0: clear on read 1: clear on write This patch allows to configure this field, through DT. Also, as suggested by "Lee Jones" renaming DT property and variable field to appropriate name. Signed-off-by: Zhao Ye Signed-off-by: Vaibhav Hiremath --- drivers/mfd/88pm800.c | 15 ++++++++++----- include/linux/mfd/88pm80x.h | 6 ++++-- 2 files changed, 14 insertions(+), 7 deletions(-) diff --git a/drivers/mfd/88pm800.c b/drivers/mfd/88pm800.c index 059f01a..c1a6306 100644 --- a/drivers/mfd/88pm800.c +++ b/drivers/mfd/88pm800.c @@ -376,7 +376,7 @@ static int device_irq_init_800(struct pm80x_chip *chip) { struct regmap *map = chip->regmap; unsigned long flags = IRQF_ONESHOT; - int data, mask, ret = -EINVAL; + int irq_clr_mode, mask, ret = -EINVAL; if (!map || !chip->irq) { dev_err(chip->dev, "incorrect parameters\n"); @@ -384,15 +384,16 @@ static int device_irq_init_800(struct pm80x_chip *chip) } /* - * irq_mode defines the way of clearing interrupt. it's read-clear by - * default. + * irq_clr_on_wr defines the way of clearing interrupt by + * read/write(0/1). It's read-clear by default. */ mask = PM800_WAKEUP2_INV_INT | PM800_WAKEUP2_INT_CLEAR | PM800_WAKEUP2_INT_MASK; - data = PM800_WAKEUP2_INT_CLEAR; - ret = regmap_update_bits(map, PM800_WAKEUP2, mask, data); + irq_clr_mode = (chip->irq_clr_on_wr) ? + PM800_WAKEUP2_INT_WRITE_CLEAR : PM800_WAKEUP2_INT_READ_CLEAR; + ret = regmap_update_bits(map, PM800_WAKEUP2, mask, irq_clr_mode); if (ret < 0) goto out; @@ -514,6 +515,7 @@ static int device_800_init(struct pm80x_chip *chip, } chip->regmap_irq_chip = &pm800_irq_chip; + chip->irq_clr_on_wr = pdata->irq_clr_on_wr; ret = device_irq_init_800(chip); if (ret < 0) { @@ -568,6 +570,9 @@ static int pm800_probe(struct i2c_client *client, dev_err(&client->dev, "failed to allocaate memory\n"); return -ENOMEM; } + + pdata->irq_clr_on_wr = of_property_read_bool(np, + "marvell,irq-clr-on-write"); } ret = pm80x_init(client); diff --git a/include/linux/mfd/88pm80x.h b/include/linux/mfd/88pm80x.h index 97cb283..94b3dcd 100644 --- a/include/linux/mfd/88pm80x.h +++ b/include/linux/mfd/88pm80x.h @@ -77,6 +77,8 @@ enum { #define PM800_WAKEUP2 (0x0E) #define PM800_WAKEUP2_INV_INT (1 << 0) #define PM800_WAKEUP2_INT_CLEAR (1 << 1) +#define PM800_WAKEUP2_INT_READ_CLEAR (0 << 1) +#define PM800_WAKEUP2_INT_WRITE_CLEAR (1 << 1) #define PM800_WAKEUP2_INT_MASK (1 << 2) #define PM800_POWER_UP_LOG (0x10) @@ -300,7 +302,7 @@ struct pm80x_chip { struct regmap_irq_chip_data *irq_data; int type; int irq; - int irq_mode; + int irq_clr_on_wr; /* '1': Clear on write, '0': Clear on read*/ unsigned long wu_flag; spinlock_t lock; }; @@ -315,7 +317,7 @@ struct pm80x_platform_data { */ struct regulator_init_data *regulators[PM800_ID_RG_MAX]; unsigned int num_regulators; - int irq_mode; /* Clear interrupt by read/write(0/1) */ + int irq_clr_on_wr; /* Clear interrupt by read/write(0/1) */ int batt_det; /* enable/disable */ int (*plat_config)(struct pm80x_chip *chip, struct pm80x_platform_data *pdata);