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[2001:1868:205::9]) by mx.google.com with ESMTPS id fu16si18010423pdb.173.2015.06.15.06.53.26 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 15 Jun 2015 06:53:27 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-arm-kernel-bounces+patch=linaro.org@lists.infradead.org designates 2001:1868:205::9 as permitted sender) client-ip=2001:1868:205::9; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1Z4Uno-0000x9-Ge; Mon, 15 Jun 2015 13:51:52 +0000 Received: from mail-lb0-f180.google.com ([209.85.217.180]) by bombadil.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1Z4Un5-0000fE-6Z for linux-arm-kernel@lists.infradead.org; Mon, 15 Jun 2015 13:51:08 +0000 Received: by lbbqq2 with SMTP id qq2so53863615lbb.3 for ; Mon, 15 Jun 2015 06:50:44 -0700 (PDT) X-Received: by 10.152.29.234 with SMTP id n10mr27418980lah.101.1434376244615; Mon, 15 Jun 2015 06:50:44 -0700 (PDT) Received: from localhost.localdomain ([85.235.11.236]) by mx.google.com with ESMTPSA id og9sm2729625lbb.22.2015.06.15.06.50.42 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 15 Jun 2015 06:50:43 -0700 (PDT) From: Linus Walleij To: linux-arm-kernel@lists.infradead.org, Mika Westerberg , Hartley Sweeten , Ryan Mallon Subject: [PATCH 3/5] ARM: ep93xx: use non-raw accessors for timer Date: Mon, 15 Jun 2015 15:50:20 +0200 Message-Id: <1434376222-4587-4-git-send-email-linus.walleij@linaro.org> X-Mailer: git-send-email 1.9.3 In-Reply-To: <1434376222-4587-1-git-send-email-linus.walleij@linaro.org> References: <1434376222-4587-1-git-send-email-linus.walleij@linaro.org> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20150615_065107_425876_AAA414AE X-CRM114-Status: GOOD ( 15.21 ) X-Spam-Score: -0.7 (/) X-Spam-Report: SpamAssassin version 3.4.0 on bombadil.infradead.org summary: Content analysis details: (-0.7 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 SPF_PASS SPF: sender matches SPF record -0.7 RCVD_IN_DNSWL_LOW RBL: Sender listed at http://www.dnswl.org/, low trust [209.85.217.180 listed in list.dnswl.org] -0.0 RCVD_IN_MSPIKE_H3 RBL: Good reputation (+3) [209.85.217.180 listed in wl.mailspike.net] -0.0 RCVD_IN_MSPIKE_WL Mailspike good senders Cc: Linus Walleij , Arnd Bergmann X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.18-1 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: , List-Help: , List-Subscribe: , MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patch=linaro.org@lists.infradead.org X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: linus.walleij@linaro.org X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.217.180 as permitted sender) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 The timer has no business using __raw accessors, in this case the readl/writel makes perfect sense as the changes really need to hit these registers before we continue. Signed-off-by: Linus Walleij --- arch/arm/mach-ep93xx/timer-ep93xx.c | 24 ++++++++++++------------ 1 file changed, 12 insertions(+), 12 deletions(-) diff --git a/arch/arm/mach-ep93xx/timer-ep93xx.c b/arch/arm/mach-ep93xx/timer-ep93xx.c index 932236b348bc..95d54ec769f6 100644 --- a/arch/arm/mach-ep93xx/timer-ep93xx.c +++ b/arch/arm/mach-ep93xx/timer-ep93xx.c @@ -55,8 +55,8 @@ static u64 notrace ep93xx_read_sched_clock(void) { u64 ret; - ret = __raw_readl(EP93XX_TIMER4_VALUE_LOW); - ret |= ((u64) (__raw_readl(EP93XX_TIMER4_VALUE_HIGH) & 0xff) << 32); + ret = readl(EP93XX_TIMER4_VALUE_LOW); + ret |= ((u64) (readl(EP93XX_TIMER4_VALUE_HIGH) & 0xff) << 32); return ret; } @@ -64,8 +64,8 @@ cycle_t ep93xx_clocksource_read(struct clocksource *c) { u64 ret; - ret = __raw_readl(EP93XX_TIMER4_VALUE_LOW); - ret |= ((u64) (__raw_readl(EP93XX_TIMER4_VALUE_HIGH) & 0xff) << 32); + ret = readl(EP93XX_TIMER4_VALUE_LOW); + ret |= ((u64) (readl(EP93XX_TIMER4_VALUE_HIGH) & 0xff) << 32); return (cycle_t) ret; } @@ -77,12 +77,12 @@ static int ep93xx_clkevt_set_next_event(unsigned long next, EP93XX_TIMER123_CONTROL_CLKSEL; /* Clear timer */ - __raw_writel(tmode, EP93XX_TIMER1_CONTROL); + writel(tmode, EP93XX_TIMER1_CONTROL); /* Set next event */ - __raw_writel(next, EP93XX_TIMER1_LOAD); - __raw_writel(tmode | EP93XX_TIMER123_CONTROL_ENABLE, - EP93XX_TIMER1_CONTROL); + writel(next, EP93XX_TIMER1_LOAD); + writel(tmode | EP93XX_TIMER123_CONTROL_ENABLE, + EP93XX_TIMER1_CONTROL); return 0; } @@ -91,7 +91,7 @@ static void ep93xx_clkevt_set_mode(enum clock_event_mode mode, struct clock_event_device *evt) { /* Disable timer */ - __raw_writel(0, EP93XX_TIMER1_CONTROL); + writel(0, EP93XX_TIMER1_CONTROL); } static struct clock_event_device ep93xx_clockevent = { @@ -107,7 +107,7 @@ static irqreturn_t ep93xx_timer_interrupt(int irq, void *dev_id) struct clock_event_device *evt = dev_id; /* Writing any value clears the timer interrupt */ - __raw_writel(1, EP93XX_TIMER1_CLEAR); + writel(1, EP93XX_TIMER1_CLEAR); evt->event_handler(evt); @@ -124,8 +124,8 @@ static struct irqaction ep93xx_timer_irq = { void __init ep93xx_timer_init(void) { /* Enable and register clocksource and sched_clock on timer 4 */ - __raw_writel(EP93XX_TIMER4_VALUE_HIGH_ENABLE, - EP93XX_TIMER4_VALUE_HIGH); + writel(EP93XX_TIMER4_VALUE_HIGH_ENABLE, + EP93XX_TIMER4_VALUE_HIGH); clocksource_mmio_init(NULL, "timer4", EP93XX_TIMER4_RATE, 200, 40, ep93xx_clocksource_read);