From patchwork Thu Jun 4 11:41:12 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Linus Walleij X-Patchwork-Id: 49524 Return-Path: X-Original-To: linaro@patches.linaro.org Delivered-To: linaro@patches.linaro.org Received: from mail-la0-f72.google.com (mail-la0-f72.google.com [209.85.215.72]) by ip-10-151-82-157.ec2.internal (Postfix) with ESMTPS id 9C4B92154F for ; Thu, 4 Jun 2015 11:43:16 +0000 (UTC) Received: by lani11 with SMTP id i11sf10867777lan.3 for ; Thu, 04 Jun 2015 04:43:15 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:delivered-to:from:to:subject:date:message-id:cc :precedence:list-id:list-unsubscribe:list-archive:list-post :list-help:list-subscribe:mime-version:content-type :content-transfer-encoding:sender:errors-to:x-original-sender :x-original-authentication-results:mailing-list; bh=F4LXOe/cPweBW1TY8JLea80owD4SP/8eaZVtjwauSiE=; b=JGsc5Souyqkxj7Gcvk+TY/1+67oW8sGzYi+INLpqNr3gR6wDQkIDh/Rm5r/Ndz/EXJ dB9FGuCuznJN285DgYSvn3Clh0V6tzRB2egUr+Qwo5FhEvun0dhHCT6jGHRcNQoA9KYl kKGAwrcJUzLqBaFBymQTikwaMev9FieQq2OFtERmWGzxLVEzrApHJk5MIh8zwBU8LKBq YkCElZFAe5Y3fV4LUkCBoG/Yw4/g0UpOYaalGMdVglJxUj0nJg6NvYTnWNMa6KShNhNh Oki673+97Racj7McEJp8Ts1nB1fT31tTWy5ScpKXb+PYAFL9FlK0ZafkUrgPbmjLf50R nJIg== X-Gm-Message-State: ALoCoQl/c4+dRMYwm0jFkqmYULIG1ZMoKsAWjiN5YEZrSFouRJQQkAzNH3ib7E3JOlUTOdkpEY18 X-Received: by 10.112.142.170 with SMTP id rx10mr34982321lbb.12.1433418195431; Thu, 04 Jun 2015 04:43:15 -0700 (PDT) X-BeenThere: patchwork-forward@linaro.org Received: by 10.152.7.146 with SMTP id j18ls82674laa.22.gmail; Thu, 04 Jun 2015 04:43:15 -0700 (PDT) X-Received: by 10.112.135.131 with SMTP id ps3mr36681863lbb.84.1433418195283; Thu, 04 Jun 2015 04:43:15 -0700 (PDT) Received: from mail-lb0-f180.google.com (mail-lb0-f180.google.com. [209.85.217.180]) by mx.google.com with ESMTPS id un5si1613483lbc.53.2015.06.04.04.43.15 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 04 Jun 2015 04:43:15 -0700 (PDT) Received-SPF: pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.217.180 as permitted sender) client-ip=209.85.217.180; Received: by lbcmx3 with SMTP id mx3so25457254lbc.1 for ; Thu, 04 Jun 2015 04:43:15 -0700 (PDT) X-Received: by 10.152.21.136 with SMTP id v8mr37022857lae.19.1433418195170; Thu, 04 Jun 2015 04:43:15 -0700 (PDT) X-Forwarded-To: patchwork-forward@linaro.org X-Forwarded-For: patch@linaro.org patchwork-forward@linaro.org Delivered-To: patch@linaro.org Received: by 10.112.108.230 with SMTP id hn6csp541136lbb; Thu, 4 Jun 2015 04:43:13 -0700 (PDT) X-Received: by 10.70.92.193 with SMTP id co1mr67342559pdb.7.1433418193210; Thu, 04 Jun 2015 04:43:13 -0700 (PDT) Received: from bombadil.infradead.org (bombadil.infradead.org. [2001:1868:205::9]) by mx.google.com with ESMTPS id o1si5518009pdd.111.2015.06.04.04.43.12 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 04 Jun 2015 04:43:13 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-arm-kernel-bounces+patch=linaro.org@lists.infradead.org designates 2001:1868:205::9 as permitted sender) client-ip=2001:1868:205::9; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1Z0TWq-0004U4-Pq; Thu, 04 Jun 2015 11:41:44 +0000 Received: from mail-la0-f43.google.com ([209.85.215.43]) by bombadil.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1Z0TWo-0004RD-Lw for linux-arm-kernel@lists.infradead.org; Thu, 04 Jun 2015 11:41:43 +0000 Received: by laei3 with SMTP id i3so29653002lae.3 for ; Thu, 04 Jun 2015 04:41:20 -0700 (PDT) X-Received: by 10.112.168.165 with SMTP id zx5mr36527759lbb.111.1433418080083; Thu, 04 Jun 2015 04:41:20 -0700 (PDT) Received: from localhost.localdomain ([85.235.11.236]) by mx.google.com with ESMTPSA id ci10sm641784lad.35.2015.06.04.04.41.17 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 04 Jun 2015 04:41:18 -0700 (PDT) From: Linus Walleij To: arm@kernel.org Subject: [PATCH] ARM64: juno: add GPIO keys Date: Thu, 4 Jun 2015 13:41:12 +0200 Message-Id: <1433418072-10319-1-git-send-email-linus.walleij@linaro.org> X-Mailer: git-send-email 1.9.3 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20150604_044142_898956_6BFAC1F7 X-CRM114-Status: GOOD ( 13.81 ) X-Spam-Score: -0.7 (/) X-Spam-Report: SpamAssassin version 3.4.0 on bombadil.infradead.org summary: Content analysis details: (-0.7 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.7 RCVD_IN_DNSWL_LOW RBL: Sender listed at http://www.dnswl.org/, low trust [209.85.215.43 listed in list.dnswl.org] -0.0 SPF_PASS SPF: sender matches SPF record -0.0 RCVD_IN_MSPIKE_H3 RBL: Good reputation (+3) [209.85.215.43 listed in wl.mailspike.net] -0.0 RCVD_IN_MSPIKE_WL Mailspike good senders Cc: Linus Walleij , linux-arm-kernel@lists.infradead.org X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.18-1 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: , List-Help: , List-Subscribe: , MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patch=linaro.org@lists.infradead.org X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: linus.walleij@linaro.org X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.217.180 as permitted sender) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 The Juno board has two keys connected to a PL061 GPIO block, in accordance to DDI0524B "ARM Versatile Express Juno Development Platform" revision 1.0, table 2-4 "GPIO (0) and GPIO (1) used for additional user key entry". By trial-and-error I found that these are connected to the two keys named "power" and "home" on the motherboard. Register the GPIO block and these two keys in the device tree using the PL061 GPIO driver and the generic gpio keys. - Map POWER, HOME, VOL+ and VOL- to the obvious input events. - Map RLOCK to KEY_SCREENLOCK/KEY_COFFEE unless someone can explain better what this is for. - Map the NMI button to KEY_SYSREQ as this is used like so in the SYSREQ debugging hack. Acked-by: Liviu Dudau Signed-off-by: Linus Walleij --- Hi ARM SoC folks, please apply this patch directly to the DT branch for ARM64. This is a resend of the v2 version with Liviu's ACK. --- arch/arm64/boot/dts/arm/juno-motherboard.dtsi | 61 +++++++++++++++++++++++++++ 1 file changed, 61 insertions(+) diff --git a/arch/arm64/boot/dts/arm/juno-motherboard.dtsi b/arch/arm64/boot/dts/arm/juno-motherboard.dtsi index 351c95bda89e..fde0cfad09de 100644 --- a/arch/arm64/boot/dts/arm/juno-motherboard.dtsi +++ b/arch/arm64/boot/dts/arm/juno-motherboard.dtsi @@ -54,6 +54,55 @@ regulator-always-on; }; + gpio_keys { + compatible = "gpio-keys"; + #address-cells = <1>; + #size-cells = <0>; + + button@1 { + debounce_interval = <50>; + wakeup = <1>; + linux,code = <116>; + label = "POWER"; + gpios = <&iofpga_gpio0 0 0x4>; + }; + button@2 { + debounce_interval = <50>; + wakeup = <1>; + linux,code = <102>; + label = "HOME"; + gpios = <&iofpga_gpio0 1 0x4>; + }; + button@3 { + debounce_interval = <50>; + wakeup = <1>; + linux,code = <152>; + label = "RLOCK"; + gpios = <&iofpga_gpio0 2 0x4>; + }; + button@4 { + debounce_interval = <50>; + wakeup = <1>; + linux,code = <115>; + label = "VOL+"; + gpios = <&iofpga_gpio0 3 0x4>; + }; + button@5 { + debounce_interval = <50>; + wakeup = <1>; + linux,code = <114>; + label = "VOL-"; + gpios = <&iofpga_gpio0 4 0x4>; + }; + button@6 { + debounce_interval = <50>; + wakeup = <1>; + linux,code = <99>; + label = "NMI"; + gpios = <&iofpga_gpio0 5 0x4>; + }; + }; + ethernet@2,00000000 { compatible = "smsc,lan9118", "smsc,lan9115"; reg = <2 0x00000000 0x10000>; @@ -148,5 +197,17 @@ clocks = <&soc_smc50mhz>; clock-names = "apb_pclk"; }; + + iofpga_gpio0: gpio@1d0000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0x1d0000 0x1000>; + interrupts = <6>; + clocks = <&soc_smc50mhz>; + clock-names = "apb_pclk"; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; }; };