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[2001:1868:205::9]) by mx.google.com with ESMTPS id ij3si15528951pbb.30.2015.05.30.21.30.40 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sat, 30 May 2015 21:30:40 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-arm-kernel-bounces+patch=linaro.org@lists.infradead.org designates 2001:1868:205::9 as permitted sender) client-ip=2001:1868:205::9; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1Yyurf-0005Lv-S1; Sun, 31 May 2015 04:28:47 +0000 Received: from mail-pd0-f169.google.com ([209.85.192.169]) by bombadil.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1YyurM-0005An-Ss for linux-arm-kernel@lists.infradead.org; Sun, 31 May 2015 04:28:29 +0000 Received: by pdbnf5 with SMTP id nf5so21871601pdb.2 for ; Sat, 30 May 2015 21:28:08 -0700 (PDT) X-Received: by 10.70.49.168 with SMTP id v8mr29165908pdn.24.1433046488361; Sat, 30 May 2015 21:28:08 -0700 (PDT) Received: from localhost ([167.160.116.87]) by mx.google.com with ESMTPSA id b10sm10173248pdo.84.2015.05.30.21.28.02 (version=TLSv1 cipher=RC4-SHA bits=128/128); Sat, 30 May 2015 21:28:07 -0700 (PDT) From: Zhichao Huang To: kvm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, kvmarm@lists.cs.columbia.edu, christoffer.dall@linaro.org, marc.zyngier@arm.com, alex.bennee@linaro.org, will.deacon@arm.com Subject: [PATCH v2 03/11] KVM: arm: enable to use the ARM_DSCR_MDBGEN macro from KVM assembly code Date: Sun, 31 May 2015 12:27:04 +0800 Message-Id: <1433046432-1824-4-git-send-email-zhichao.huang@linaro.org> X-Mailer: git-send-email 1.9.5.msysgit.1 In-Reply-To: <1433046432-1824-1-git-send-email-zhichao.huang@linaro.org> References: <1433046432-1824-1-git-send-email-zhichao.huang@linaro.org> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20150530_212829_044138_55B45117 X-CRM114-Status: UNSURE ( 8.96 ) X-CRM114-Notice: Please train this message. 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X-Original-Sender: zhichao.huang@linaro.org X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.215.50 as permitted sender) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 Add #ifndef __ASSEMBLY__ in hw_breakpoint.h, in order to use the ARM_DSCR_MDBGEN macro from KVM assembly code. Signed-off-by: Zhichao Huang Reviewed-by: Alex Bennée --- arch/arm/include/asm/hw_breakpoint.h | 54 +++++++++++++++++++----------------- 1 file changed, 29 insertions(+), 25 deletions(-) diff --git a/arch/arm/include/asm/hw_breakpoint.h b/arch/arm/include/asm/hw_breakpoint.h index 8e427c7..f2f4c61 100644 --- a/arch/arm/include/asm/hw_breakpoint.h +++ b/arch/arm/include/asm/hw_breakpoint.h @@ -3,6 +3,8 @@ #ifdef __KERNEL__ +#ifndef __ASSEMBLY__ + struct task_struct; #ifdef CONFIG_HAVE_HW_BREAKPOINT @@ -44,6 +46,33 @@ static inline void decode_ctrl_reg(u32 reg, ctrl->mismatch = reg & 0x1; } +struct notifier_block; +struct perf_event; +struct pmu; + +extern struct pmu perf_ops_bp; +extern int arch_bp_generic_fields(struct arch_hw_breakpoint_ctrl ctrl, + int *gen_len, int *gen_type); +extern int arch_check_bp_in_kernelspace(struct perf_event *bp); +extern int arch_validate_hwbkpt_settings(struct perf_event *bp); +extern int hw_breakpoint_exceptions_notify(struct notifier_block *unused, + unsigned long val, void *data); + +extern u8 arch_get_debug_arch(void); +extern u8 arch_get_max_wp_len(void); +extern void clear_ptrace_hw_breakpoint(struct task_struct *tsk); + +int arch_install_hw_breakpoint(struct perf_event *bp); +void arch_uninstall_hw_breakpoint(struct perf_event *bp); +void hw_breakpoint_pmu_read(struct perf_event *bp); +int hw_breakpoint_slots(int type); + +#else +static inline void clear_ptrace_hw_breakpoint(struct task_struct *tsk) {} + +#endif /* CONFIG_HAVE_HW_BREAKPOINT */ +#endif /* __ASSEMBLY */ + /* Debug architecture numbers. */ #define ARM_DEBUG_ARCH_RESERVED 0 /* In case of ptrace ABI updates. */ #define ARM_DEBUG_ARCH_V6 1 @@ -110,30 +139,5 @@ static inline void decode_ctrl_reg(u32 reg, asm volatile("mcr p14, 0, %0, " #N "," #M ", " #OP2 : : "r" (VAL));\ } while (0) -struct notifier_block; -struct perf_event; -struct pmu; - -extern struct pmu perf_ops_bp; -extern int arch_bp_generic_fields(struct arch_hw_breakpoint_ctrl ctrl, - int *gen_len, int *gen_type); -extern int arch_check_bp_in_kernelspace(struct perf_event *bp); -extern int arch_validate_hwbkpt_settings(struct perf_event *bp); -extern int hw_breakpoint_exceptions_notify(struct notifier_block *unused, - unsigned long val, void *data); - -extern u8 arch_get_debug_arch(void); -extern u8 arch_get_max_wp_len(void); -extern void clear_ptrace_hw_breakpoint(struct task_struct *tsk); - -int arch_install_hw_breakpoint(struct perf_event *bp); -void arch_uninstall_hw_breakpoint(struct perf_event *bp); -void hw_breakpoint_pmu_read(struct perf_event *bp); -int hw_breakpoint_slots(int type); - -#else -static inline void clear_ptrace_hw_breakpoint(struct task_struct *tsk) {} - -#endif /* CONFIG_HAVE_HW_BREAKPOINT */ #endif /* __KERNEL__ */ #endif /* _ARM_HW_BREAKPOINT_H */