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[2001:1868:205::9]) by mx.google.com with ESMTPS id sc1si19910905pbc.155.2015.05.26.01.42.55 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 26 May 2015 01:42:56 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-arm-kernel-bounces+patch=linaro.org@lists.infradead.org designates 2001:1868:205::9 as permitted sender) client-ip=2001:1868:205::9; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1YxAQN-0006p0-S8; Tue, 26 May 2015 08:41:23 +0000 Received: from mail-la0-f50.google.com ([209.85.215.50]) by bombadil.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1YxAQI-0006hi-Gn for linux-arm-kernel@lists.infradead.org; Tue, 26 May 2015 08:41:19 +0000 Received: by lami4 with SMTP id i4so62595071lam.0 for ; Tue, 26 May 2015 01:40:56 -0700 (PDT) X-Received: by 10.112.85.204 with SMTP id j12mr16276706lbz.47.1432629656313; Tue, 26 May 2015 01:40:56 -0700 (PDT) Received: from localhost.localdomain ([85.235.11.236]) by mx.google.com with ESMTPSA id f5sm1084510lbd.41.2015.05.26.01.40.54 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 26 May 2015 01:40:55 -0700 (PDT) From: Linus Walleij To: linux-arm-kernel@lists.infradead.org, Liviu Dudau , Daniel Thompson Subject: [PATCH 1/2 v2] ARM64: juno: add GPIO keys Date: Tue, 26 May 2015 10:40:50 +0200 Message-Id: <1432629650-19559-1-git-send-email-linus.walleij@linaro.org> X-Mailer: git-send-email 1.9.3 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20150526_014118_768335_756554F5 X-CRM114-Status: GOOD ( 15.68 ) X-Spam-Score: -0.7 (/) X-Spam-Report: SpamAssassin version 3.4.0 on bombadil.infradead.org summary: Content analysis details: (-0.7 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.7 RCVD_IN_DNSWL_LOW RBL: Sender listed at http://www.dnswl.org/, low trust [209.85.215.50 listed in list.dnswl.org] -0.0 SPF_PASS SPF: sender matches SPF record -0.0 RCVD_IN_MSPIKE_H3 RBL: Good reputation (+3) [209.85.215.50 listed in wl.mailspike.net] -0.0 RCVD_IN_MSPIKE_WL Mailspike good senders Cc: Catalin Marinas , Linus Walleij , Will Deacon X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.18-1 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: , List-Help: , List-Subscribe: , MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patch=linaro.org@lists.infradead.org X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: linus.walleij@linaro.org X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.215.46 as permitted sender) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 The Juno board has two keys connected to a PL061 GPIO block, in accordance to DDI0524B "ARM Versatile Express Juno Development Platform" revision 1.0, table 2-4 "GPIO (0) and GPIO (1) used for additional user key entry". By trial-and-error I found that these are connected to the two keys named "power" and "home" on the motherboard. Register the GPIO block and these two keys in the device tree using the PL061 GPIO driver and the generic gpio keys. - Map POWER, HOME, VOL+ and VOL- to the obvious input events. - Map RLOCK to KEY_SCREENLOCK/KEY_COFFEE unless someone can explain better what this is for. - Map the NMI button to KEY_SYSREQ as this is used like so in the SYSREQ debugging hack. Signed-off-by: Linus Walleij --- ChangeLog v1->v2: - Register the GPIO block at 0x1d0000 as gpio0, as it turns out there is an unused GPIO block at 0x1e0000 as well. - Label using capital letters. - Map all 6 keys. Only the two highest GPIO lines are unused. - Daniel: please look at this: the Juno has an NMI button, not on the primary IRQ controller (GIC) but on a cascaded GPIO controller. I have waited for this to happen, what are your thoughts about the possibilities to handle this with the priority-escalation trick you were devising for GIC's with FIQ stolen by TrustZone? As the Juno is a typical server design I suspect this is what we have to deal with for the "server-with-an-NMI-pushbutton" use case. --- arch/arm64/boot/dts/arm/juno-motherboard.dtsi | 61 +++++++++++++++++++++++++++ 1 file changed, 61 insertions(+) diff --git a/arch/arm64/boot/dts/arm/juno-motherboard.dtsi b/arch/arm64/boot/dts/arm/juno-motherboard.dtsi index 351c95bda89e..fde0cfad09de 100644 --- a/arch/arm64/boot/dts/arm/juno-motherboard.dtsi +++ b/arch/arm64/boot/dts/arm/juno-motherboard.dtsi @@ -54,6 +54,55 @@ regulator-always-on; }; + gpio_keys { + compatible = "gpio-keys"; + #address-cells = <1>; + #size-cells = <0>; + + button@1 { + debounce_interval = <50>; + wakeup = <1>; + linux,code = <116>; + label = "POWER"; + gpios = <&iofpga_gpio0 0 0x4>; + }; + button@2 { + debounce_interval = <50>; + wakeup = <1>; + linux,code = <102>; + label = "HOME"; + gpios = <&iofpga_gpio0 1 0x4>; + }; + button@3 { + debounce_interval = <50>; + wakeup = <1>; + linux,code = <152>; + label = "RLOCK"; + gpios = <&iofpga_gpio0 2 0x4>; + }; + button@4 { + debounce_interval = <50>; + wakeup = <1>; + linux,code = <115>; + label = "VOL+"; + gpios = <&iofpga_gpio0 3 0x4>; + }; + button@5 { + debounce_interval = <50>; + wakeup = <1>; + linux,code = <114>; + label = "VOL-"; + gpios = <&iofpga_gpio0 4 0x4>; + }; + button@6 { + debounce_interval = <50>; + wakeup = <1>; + linux,code = <99>; + label = "NMI"; + gpios = <&iofpga_gpio0 5 0x4>; + }; + }; + ethernet@2,00000000 { compatible = "smsc,lan9118", "smsc,lan9115"; reg = <2 0x00000000 0x10000>; @@ -148,5 +197,17 @@ clocks = <&soc_smc50mhz>; clock-names = "apb_pclk"; }; + + iofpga_gpio0: gpio@1d0000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0x1d0000 0x1000>; + interrupts = <6>; + clocks = <&soc_smc50mhz>; + clock-names = "apb_pclk"; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; }; };