From patchwork Fri May 22 15:29:55 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Shawn Guo X-Patchwork-Id: 48907 Return-Path: X-Original-To: linaro@patches.linaro.org Delivered-To: linaro@patches.linaro.org Received: from mail-la0-f71.google.com (mail-la0-f71.google.com [209.85.215.71]) by ip-10-151-82-157.ec2.internal (Postfix) with ESMTPS id 9FBD821411 for ; Fri, 22 May 2015 15:53:11 +0000 (UTC) Received: by labcd2 with SMTP id cd2sf6358625lab.0 for ; Fri, 22 May 2015 08:53:10 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:delivered-to:from:to:subject:date:message-id :in-reply-to:references:cc:precedence:list-id:list-unsubscribe :list-archive:list-post:list-help:list-subscribe:mime-version :content-type:content-transfer-encoding:sender:errors-to :x-original-sender:x-original-authentication-results:mailing-list; bh=e8+rPQ52fbutk8EwMjiC3ZAr9wq/1Rv4Duppz2+k8B8=; b=iM9ox08UUbVf5LFwPYLG19s3eUzseyAjnS1rjec3IHtPed1KmgWHxth2qzSnyTelpp oKN+h2pwx5ysnHKgSsS10cZmpRmIOtxO1xraHLFk9V74RuFQPtEENYaA4avQaqlXAYHP iAwLoIb2kOZzSYQMAEkYKEPCNqk9Umur/yPLGWw5TNPFrh2r9RtEe68OyhEOURUbZ8cC MYSLHU16wDX6CG9ciJuTJYSYCU/OKivDTGaF4reZvM2QORraop6aGKHarhbuJ9hvpkY6 ApmpYIy9AZ08TxsMT1XW2VGoeqZGwTTl7UENRd3AO9VM9uyUiHd/a707W8Xm2RF709Qy TE4A== X-Gm-Message-State: ALoCoQmuBSxJKaUb+0TYCRsUgBn7cPOiLqzj+qVpTBsld8jXoR5MXYmdFI0CedbvXXHJzXskYZeu X-Received: by 10.112.148.101 with SMTP id tr5mr860642lbb.13.1432309990572; Fri, 22 May 2015 08:53:10 -0700 (PDT) X-BeenThere: patchwork-forward@linaro.org Received: by 10.152.22.99 with SMTP id c3ls493449laf.96.gmail; Fri, 22 May 2015 08:53:10 -0700 (PDT) X-Received: by 10.152.21.136 with SMTP id v8mr6980783lae.19.1432309990423; Fri, 22 May 2015 08:53:10 -0700 (PDT) Received: from mail-lb0-f179.google.com (mail-lb0-f179.google.com. [209.85.217.179]) by mx.google.com with ESMTPS id ln2si1647787lac.106.2015.05.22.08.53.10 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 22 May 2015 08:53:10 -0700 (PDT) Received-SPF: pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.217.179 as permitted sender) client-ip=209.85.217.179; Received: by lbbqq2 with SMTP id qq2so15819139lbb.3 for ; Fri, 22 May 2015 08:53:10 -0700 (PDT) X-Received: by 10.112.163.168 with SMTP id yj8mr6969848lbb.36.1432309990282; Fri, 22 May 2015 08:53:10 -0700 (PDT) X-Forwarded-To: patchwork-forward@linaro.org X-Forwarded-For: patch@linaro.org patchwork-forward@linaro.org Delivered-To: patch@linaro.org Received: by 10.112.108.230 with SMTP id hn6csp1507401lbb; Fri, 22 May 2015 08:53:09 -0700 (PDT) X-Received: by 10.70.37.69 with SMTP id w5mr16668254pdj.123.1432309988549; Fri, 22 May 2015 08:53:08 -0700 (PDT) Received: from bombadil.infradead.org (bombadil.infradead.org. [2001:1868:205::9]) by mx.google.com with ESMTPS id k4si3925580pbq.230.2015.05.22.08.53.07 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 22 May 2015 08:53:08 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-arm-kernel-bounces+patch=linaro.org@lists.infradead.org designates 2001:1868:205::9 as permitted sender) client-ip=2001:1868:205::9; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1YvpDM-00008y-Sv; Fri, 22 May 2015 15:50:24 +0000 Received: from mail-pa0-f49.google.com ([209.85.220.49]) by bombadil.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1Yvovs-0006UM-R2 for linux-arm-kernel@lists.infradead.org; Fri, 22 May 2015 15:32:22 +0000 Received: by pacwv17 with SMTP id wv17so22361846pac.2 for ; Fri, 22 May 2015 08:31:58 -0700 (PDT) X-Received: by 10.66.230.130 with SMTP id sy2mr16744923pac.157.1432308718122; Fri, 22 May 2015 08:31:58 -0700 (PDT) Received: from localhost.localdomain ([107.6.117.178]) by mx.google.com with ESMTPSA id as1sm2474485pbc.39.2015.05.22.08.31.53 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 22 May 2015 08:31:57 -0700 (PDT) From: Shawn Guo To: linux-arm-kernel@lists.infradead.org Subject: [PATCH v2 08/12] ARM: imx: define gpt register offset per device type Date: Fri, 22 May 2015 23:29:55 +0800 Message-Id: <1432308599-28643-9-git-send-email-shawn.guo@linaro.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1432308599-28643-1-git-send-email-shawn.guo@linaro.org> References: <1432308599-28643-1-git-send-email-shawn.guo@linaro.org> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20150522_083220_965268_B583A1D0 X-CRM114-Status: GOOD ( 13.43 ) X-Spam-Score: -0.7 (/) X-Spam-Report: SpamAssassin version 3.4.0 on bombadil.infradead.org summary: Content analysis details: (-0.7 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.7 RCVD_IN_DNSWL_LOW RBL: Sender listed at http://www.dnswl.org/, low trust [209.85.220.49 listed in list.dnswl.org] -0.0 RCVD_IN_MSPIKE_H3 RBL: Good reputation (+3) [209.85.220.49 listed in wl.mailspike.net] -0.0 SPF_PASS SPF: sender matches SPF record -0.0 RCVD_IN_MSPIKE_WL Mailspike good senders Cc: Shawn Guo , Daniel Lezcano , Arnd Bergmann , kernel@pengutronix.de, Shenwei Wang X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.18-1 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: , List-Help: , List-Subscribe: , MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patch=linaro.org@lists.infradead.org X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: shawn.guo@linaro.org X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.217.179 as permitted sender) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 It defines offset of gpt registers TSTAT, TCN and TCMP per device type in imx_gpt_data, so that these registers can be accessed in an way without timer_is_v2() checking. Signed-off-by: Shawn Guo --- arch/arm/mach-imx/time.c | 31 ++++++++++++++++++++----------- 1 file changed, 20 insertions(+), 11 deletions(-) diff --git a/arch/arm/mach-imx/time.c b/arch/arm/mach-imx/time.c index c4692e0a944f..da1ad20d2c1d 100644 --- a/arch/arm/mach-imx/time.c +++ b/arch/arm/mach-imx/time.c @@ -96,6 +96,9 @@ struct imx_timer { }; struct imx_gpt_data { + int reg_tstat; + int reg_tcn; + int reg_tcmp; void (*gpt_setup_tctl)(struct imx_timer *imxtm); int (*set_next_event)(unsigned long evt, struct clock_event_device *ced); @@ -159,7 +162,7 @@ static unsigned long imx_read_current_timer(void) static int __init mxc_clocksource_init(struct imx_timer *imxtm) { unsigned int c = clk_get_rate(imxtm->clk_per); - void __iomem *reg = imxtm->base + (timer_is_v2() ? V2_TCN : MX1_2_TCN); + void __iomem *reg = imxtm->base + imxtm->gpt->reg_tcn; imx_delay_timer.read_current_timer = &imx_read_current_timer; imx_delay_timer.freq = c; @@ -227,13 +230,9 @@ static void mxc_set_mode(enum clock_event_mode mode, gpt_irq_disable(); if (mode != imxtm->cem) { + u32 tcn = readl_relaxed(imxtm->base + imxtm->gpt->reg_tcn); /* Set event time into far-far future */ - if (timer_is_v2()) - writel_relaxed(readl_relaxed(timer_base + V2_TCN) - 3, - timer_base + V2_TCMP); - else - writel_relaxed(readl_relaxed(timer_base + MX1_2_TCN) - 3, - timer_base + MX1_2_TCMP); + writel_relaxed(tcn - 3, imxtm->base + imxtm->gpt->reg_tcmp); /* Clear pending interrupt */ gpt_irq_acknowledge(); @@ -279,12 +278,10 @@ static void mxc_set_mode(enum clock_event_mode mode, static irqreturn_t mxc_timer_interrupt(int irq, void *dev_id) { struct clock_event_device *ced = dev_id; + struct imx_timer *imxtm = to_imx_timer(ced); uint32_t tstat; - if (timer_is_v2()) - tstat = readl_relaxed(timer_base + V2_TSTAT); - else - tstat = readl_relaxed(timer_base + MX1_2_TSTAT); + tstat = readl_relaxed(imxtm->base + imxtm->gpt->reg_tstat); gpt_irq_acknowledge(); @@ -357,21 +354,33 @@ static void imx6dl_gpt_setup_tctl(struct imx_timer *imxtm) } static const struct imx_gpt_data imx1_gpt_data = { + .reg_tstat = MX1_2_TSTAT, + .reg_tcn = MX1_2_TCN, + .reg_tcmp = MX1_2_TCMP, .gpt_setup_tctl = imx1_gpt_setup_tctl, .set_next_event = mx1_2_set_next_event, }; static const struct imx_gpt_data imx21_gpt_data = { + .reg_tstat = MX1_2_TSTAT, + .reg_tcn = MX1_2_TCN, + .reg_tcmp = MX1_2_TCMP, .gpt_setup_tctl = imx21_gpt_setup_tctl, .set_next_event = mx1_2_set_next_event, }; static const struct imx_gpt_data imx31_gpt_data = { + .reg_tstat = V2_TSTAT, + .reg_tcn = V2_TCN, + .reg_tcmp = V2_TCMP, .gpt_setup_tctl = imx31_gpt_setup_tctl, .set_next_event = v2_set_next_event, }; static const struct imx_gpt_data imx6dl_gpt_data = { + .reg_tstat = V2_TSTAT, + .reg_tcn = V2_TCN, + .reg_tcmp = V2_TCMP, .gpt_setup_tctl = imx6dl_gpt_setup_tctl, .set_next_event = v2_set_next_event, };