From patchwork Fri May 22 15:29:48 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Shawn Guo X-Patchwork-Id: 48896 Return-Path: X-Original-To: linaro@patches.linaro.org Delivered-To: linaro@patches.linaro.org Received: from mail-wg0-f70.google.com (mail-wg0-f70.google.com [74.125.82.70]) by ip-10-151-82-157.ec2.internal (Postfix) with ESMTPS id 192C521411 for ; Fri, 22 May 2015 15:34:56 +0000 (UTC) Received: by wgwl7 with SMTP id l7sf6279257wgw.0 for ; Fri, 22 May 2015 08:34:55 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:delivered-to:from:to:subject:date:message-id :in-reply-to:references:cc:precedence:list-id:list-unsubscribe :list-archive:list-post:list-help:list-subscribe:mime-version :content-type:content-transfer-encoding:sender:errors-to :x-original-sender:x-original-authentication-results:mailing-list; bh=JEnZh0LWr8u2icqmjqOfhLahLkACQ3iuYPWVN+GewtI=; b=VToKyRaNaludqx+TGsiRw4BZ2u6VPrIP969HbpSDQyq1II47LwZdWdTMUa+NpXqoqM VDV61ks6a05YoSILZz2wdDmywFgnJz7SDqasRtwLmFzmVvvPCqsySUAE0vOybQOpyz0f ilgD45j5jDkOKfD611sQsBQTwxGyr3FluuJmC9cMrvtf/0xIRaQI1svPHmkxz9HFOZJ5 RoXXKzStzUwlhHzPJWoOmHHBTwpDuB4rHjRqQH/sEDcq9GIYKhxF2wsQYkYPuWDuPvr+ +wMQaSsTxyxuRD+0JQP0i8+S+CFs+P6OcFqc2NHdmWmYue4x9FXrlwtoKxy/K0BtbZJ6 ZWlw== X-Gm-Message-State: ALoCoQm1+WTIQBihwmOOtkfNa97vSBrLdWdRS0k06hidxIgZetKncd/MkAjvXlyjUxF0+MIxUk3L X-Received: by 10.180.85.129 with SMTP id h1mr4466103wiz.6.1432308895320; Fri, 22 May 2015 08:34:55 -0700 (PDT) X-BeenThere: patchwork-forward@linaro.org Received: by 10.152.3.133 with SMTP id c5ls437251lac.68.gmail; Fri, 22 May 2015 08:34:55 -0700 (PDT) X-Received: by 10.152.37.37 with SMTP id v5mr6752444laj.11.1432308895152; Fri, 22 May 2015 08:34:55 -0700 (PDT) Received: from mail-la0-f51.google.com (mail-la0-f51.google.com. [209.85.215.51]) by mx.google.com with ESMTPS id ev1si1641075lbc.0.2015.05.22.08.34.55 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 22 May 2015 08:34:55 -0700 (PDT) Received-SPF: pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.215.51 as permitted sender) client-ip=209.85.215.51; Received: by lagv1 with SMTP id v1so15154760lag.3 for ; Fri, 22 May 2015 08:34:55 -0700 (PDT) X-Received: by 10.152.206.75 with SMTP id lm11mr6759780lac.41.1432308895044; Fri, 22 May 2015 08:34:55 -0700 (PDT) X-Forwarded-To: patchwork-forward@linaro.org X-Forwarded-For: patch@linaro.org patchwork-forward@linaro.org Delivered-To: patch@linaro.org Received: by 10.112.108.230 with SMTP id hn6csp1495341lbb; Fri, 22 May 2015 08:34:53 -0700 (PDT) X-Received: by 10.70.118.5 with SMTP id ki5mr16889478pdb.6.1432308893097; Fri, 22 May 2015 08:34:53 -0700 (PDT) Received: from bombadil.infradead.org (bombadil.infradead.org. [2001:1868:205::9]) by mx.google.com with ESMTPS id ex5si3926078pac.119.2015.05.22.08.34.52 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 22 May 2015 08:34:53 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-arm-kernel-bounces+patch=linaro.org@lists.infradead.org designates 2001:1868:205::9 as permitted sender) client-ip=2001:1868:205::9; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1YvowP-00071G-VN; Fri, 22 May 2015 15:32:54 +0000 Received: from mail-pa0-f48.google.com ([209.85.220.48]) by bombadil.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1YvovG-00064t-Fa for linux-arm-kernel@lists.infradead.org; Fri, 22 May 2015 15:31:43 +0000 Received: by pabru16 with SMTP id ru16so22417198pab.1 for ; Fri, 22 May 2015 08:31:20 -0700 (PDT) X-Received: by 10.68.113.194 with SMTP id ja2mr16317622pbb.163.1432308680860; Fri, 22 May 2015 08:31:20 -0700 (PDT) Received: from localhost.localdomain ([107.6.117.178]) by mx.google.com with ESMTPSA id as1sm2474485pbc.39.2015.05.22.08.31.15 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 22 May 2015 08:31:20 -0700 (PDT) From: Shawn Guo To: linux-arm-kernel@lists.infradead.org Subject: [PATCH v2 01/12] ARM: imx: use relaxed IO accessor in timer driver Date: Fri, 22 May 2015 23:29:48 +0800 Message-Id: <1432308599-28643-2-git-send-email-shawn.guo@linaro.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1432308599-28643-1-git-send-email-shawn.guo@linaro.org> References: <1432308599-28643-1-git-send-email-shawn.guo@linaro.org> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20150522_083142_646895_BFCFEF3F X-CRM114-Status: GOOD ( 16.16 ) X-Spam-Score: -1.8 (-) X-Spam-Report: SpamAssassin version 3.4.0 on bombadil.infradead.org summary: Content analysis details: (-1.8 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.7 RCVD_IN_DNSWL_LOW RBL: Sender listed at http://www.dnswl.org/, low trust [209.85.220.48 listed in list.dnswl.org] -0.0 SPF_PASS SPF: sender matches SPF record -1.1 RCVD_IN_MSPIKE_H2 RBL: Average reputation (+2) [209.85.220.48 listed in wl.mailspike.net] Cc: Shawn Guo , Daniel Lezcano , Arnd Bergmann , kernel@pengutronix.de, Shenwei Wang X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.18-1 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: , List-Help: , List-Subscribe: , MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patch=linaro.org@lists.infradead.org X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: shawn.guo@linaro.org X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.215.51 as permitted sender) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 Replace the __raw_readl/__raw_writel with readl_relaxed/writel_relaxed which is endian-safe, as a step of moving the driver code into folder drivers/clocksource. Signed-off-by: Shawn Guo --- arch/arm/mach-imx/time.c | 48 ++++++++++++++++++++++++------------------------ 1 file changed, 24 insertions(+), 24 deletions(-) diff --git a/arch/arm/mach-imx/time.c b/arch/arm/mach-imx/time.c index ab5ee1c445f3..376d5d8ccfb8 100644 --- a/arch/arm/mach-imx/time.c +++ b/arch/arm/mach-imx/time.c @@ -91,19 +91,19 @@ static inline void gpt_irq_disable(void) unsigned int tmp; if (timer_is_v2()) - __raw_writel(0, timer_base + V2_IR); + writel_relaxed(0, timer_base + V2_IR); else { - tmp = __raw_readl(timer_base + MXC_TCTL); - __raw_writel(tmp & ~MX1_2_TCTL_IRQEN, timer_base + MXC_TCTL); + tmp = readl_relaxed(timer_base + MXC_TCTL); + writel_relaxed(tmp & ~MX1_2_TCTL_IRQEN, timer_base + MXC_TCTL); } } static inline void gpt_irq_enable(void) { if (timer_is_v2()) - __raw_writel(1<<0, timer_base + V2_IR); + writel_relaxed(1<<0, timer_base + V2_IR); else { - __raw_writel(__raw_readl(timer_base + MXC_TCTL) | MX1_2_TCTL_IRQEN, + writel_relaxed(readl_relaxed(timer_base + MXC_TCTL) | MX1_2_TCTL_IRQEN, timer_base + MXC_TCTL); } } @@ -112,26 +112,26 @@ static void gpt_irq_acknowledge(void) { if (timer_is_v1()) { if (cpu_is_mx1()) - __raw_writel(0, timer_base + MX1_2_TSTAT); + writel_relaxed(0, timer_base + MX1_2_TSTAT); else - __raw_writel(MX2_TSTAT_CAPT | MX2_TSTAT_COMP, + writel_relaxed(MX2_TSTAT_CAPT | MX2_TSTAT_COMP, timer_base + MX1_2_TSTAT); } else if (timer_is_v2()) - __raw_writel(V2_TSTAT_OF1, timer_base + V2_TSTAT); + writel_relaxed(V2_TSTAT_OF1, timer_base + V2_TSTAT); } static void __iomem *sched_clock_reg; static u64 notrace mxc_read_sched_clock(void) { - return sched_clock_reg ? __raw_readl(sched_clock_reg) : 0; + return sched_clock_reg ? readl_relaxed(sched_clock_reg) : 0; } static struct delay_timer imx_delay_timer; static unsigned long imx_read_current_timer(void) { - return __raw_readl(sched_clock_reg); + return readl_relaxed(sched_clock_reg); } static int __init mxc_clocksource_init(struct clk *timer_clk) @@ -157,11 +157,11 @@ static int mx1_2_set_next_event(unsigned long evt, { unsigned long tcmp; - tcmp = __raw_readl(timer_base + MX1_2_TCN) + evt; + tcmp = readl_relaxed(timer_base + MX1_2_TCN) + evt; - __raw_writel(tcmp, timer_base + MX1_2_TCMP); + writel_relaxed(tcmp, timer_base + MX1_2_TCMP); - return (int)(tcmp - __raw_readl(timer_base + MX1_2_TCN)) < 0 ? + return (int)(tcmp - readl_relaxed(timer_base + MX1_2_TCN)) < 0 ? -ETIME : 0; } @@ -170,12 +170,12 @@ static int v2_set_next_event(unsigned long evt, { unsigned long tcmp; - tcmp = __raw_readl(timer_base + V2_TCN) + evt; + tcmp = readl_relaxed(timer_base + V2_TCN) + evt; - __raw_writel(tcmp, timer_base + V2_TCMP); + writel_relaxed(tcmp, timer_base + V2_TCMP); return evt < 0x7fffffff && - (int)(tcmp - __raw_readl(timer_base + V2_TCN)) < 0 ? + (int)(tcmp - readl_relaxed(timer_base + V2_TCN)) < 0 ? -ETIME : 0; } @@ -206,10 +206,10 @@ static void mxc_set_mode(enum clock_event_mode mode, if (mode != clockevent_mode) { /* Set event time into far-far future */ if (timer_is_v2()) - __raw_writel(__raw_readl(timer_base + V2_TCN) - 3, + writel_relaxed(readl_relaxed(timer_base + V2_TCN) - 3, timer_base + V2_TCMP); else - __raw_writel(__raw_readl(timer_base + MX1_2_TCN) - 3, + writel_relaxed(readl_relaxed(timer_base + MX1_2_TCN) - 3, timer_base + MX1_2_TCMP); /* Clear pending interrupt */ @@ -259,9 +259,9 @@ static irqreturn_t mxc_timer_interrupt(int irq, void *dev_id) uint32_t tstat; if (timer_is_v2()) - tstat = __raw_readl(timer_base + V2_TSTAT); + tstat = readl_relaxed(timer_base + V2_TSTAT); else - tstat = __raw_readl(timer_base + MX1_2_TSTAT); + tstat = readl_relaxed(timer_base + MX1_2_TSTAT); gpt_irq_acknowledge(); @@ -316,8 +316,8 @@ static void __init _mxc_timer_init(int irq, * Initialise to a known state (all timers off, and timing reset) */ - __raw_writel(0, timer_base + MXC_TCTL); - __raw_writel(0, timer_base + MXC_TPRER); /* see datasheet note */ + writel_relaxed(0, timer_base + MXC_TCTL); + writel_relaxed(0, timer_base + MXC_TPRER); /* see datasheet note */ if (timer_is_v2()) { tctl_val = V2_TCTL_FRR | V2_TCTL_WAITEN | MXC_TCTL_TEN; @@ -325,7 +325,7 @@ static void __init _mxc_timer_init(int irq, tctl_val |= V2_TCTL_CLK_OSC_DIV8; if (cpu_is_imx6dl() || cpu_is_imx6sx()) { /* 24 / 8 = 3 MHz */ - __raw_writel(7 << V2_TPRER_PRE24M, + writel_relaxed(7 << V2_TPRER_PRE24M, timer_base + MXC_TPRER); tctl_val |= V2_TCTL_24MEN; } @@ -336,7 +336,7 @@ static void __init _mxc_timer_init(int irq, tctl_val = MX1_2_TCTL_FRR | MX1_2_TCTL_CLK_PCLK1 | MXC_TCTL_TEN; } - __raw_writel(tctl_val, timer_base + MXC_TCTL); + writel_relaxed(tctl_val, timer_base + MXC_TCTL); /* init and register the timer to the framework */ mxc_clocksource_init(clk_per);