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[209.132.180.67]) by mx.google.com with ESMTP id w2si22164137pde.152.2015.05.19.09.58.15; Tue, 19 May 2015 09:58:32 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753976AbbESQ5o (ORCPT + 28 others); Tue, 19 May 2015 12:57:44 -0400 Received: from mail-pd0-f182.google.com ([209.85.192.182]:36710 "EHLO mail-pd0-f182.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751704AbbESQz7 (ORCPT ); Tue, 19 May 2015 12:55:59 -0400 Received: by pdfh10 with SMTP id h10so32906168pdf.3 for ; Tue, 19 May 2015 09:55:59 -0700 (PDT) X-Received: by 10.68.226.37 with SMTP id rp5mr54906758pbc.21.1432054559006; Tue, 19 May 2015 09:55:59 -0700 (PDT) Received: from t430.cg.shawcable.net ([184.64.168.246]) by mx.google.com with ESMTPSA id rx6sm11817453pbc.54.2015.05.19.09.55.57 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 19 May 2015 09:55:58 -0700 (PDT) From: Mathieu Poirier To: gregkh@linuxfoundation.org Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, zhang.chunyan@linaro.org, kaixu.xia@linaro.org, mathieu.poirier@linaro.org Subject: [PATCH 14/16] coresight: document the bindings for the ATCLK Date: Tue, 19 May 2015 10:55:19 -0600 Message-Id: <1432054521-24807-15-git-send-email-mathieu.poirier@linaro.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1432054521-24807-1-git-send-email-mathieu.poirier@linaro.org> References: <1432054521-24807-1-git-send-email-mathieu.poirier@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: list List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: mathieu.poirier@linaro.org X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.215.48 as permitted sender) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , From: Linus Walleij Put in a blurb in the device tree bindings indicating that coresight blocks may have an optional ATCLK. Signed-off-by: Linus Walleij Signed-off-by: Mathieu Poirier --- Documentation/devicetree/bindings/arm/coresight.txt | 13 ++++++++----- 1 file changed, 8 insertions(+), 5 deletions(-) diff --git a/Documentation/devicetree/bindings/arm/coresight.txt b/Documentation/devicetree/bindings/arm/coresight.txt index 88602b75418e..8711c1065479 100644 --- a/Documentation/devicetree/bindings/arm/coresight.txt +++ b/Documentation/devicetree/bindings/arm/coresight.txt @@ -21,11 +21,14 @@ its hardware characteristcs. * reg: physical base address and length of the register set(s) of the component. - * clocks: the clock associated to this component. - - * clock-names: the name of the clock as referenced by the code. - Since we are using the AMBA framework, the name should be - "apb_pclk". + * clocks: the clocks associated to this component. + + * clock-names: the name of the clocks referenced by the code. + Since we are using the AMBA framework, the name of the clock + providing the interconnect should be "apb_pclk", and some + coresight blocks also have an additional clock "atclk", which + clocks the core of that coresight component. The latter clock + is optional. * port or ports: The representation of the component's port layout using the generic DT graph presentation found in