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[2001:1868:205::9]) by mx.google.com with ESMTPS id hu6si1465806pac.153.2015.05.15.01.17.45 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 15 May 2015 01:17:46 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-arm-kernel-bounces+patch=linaro.org@lists.infradead.org designates 2001:1868:205::9 as permitted sender) client-ip=2001:1868:205::9; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1YtAmP-0000I8-NB; Fri, 15 May 2015 08:15:37 +0000 Received: from mail.kernel.org ([198.145.29.136]) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1YtAkO-0006Jh-Gx for linux-arm-kernel@lists.infradead.org; Fri, 15 May 2015 08:13:35 +0000 Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 994B820412; Fri, 15 May 2015 08:13:10 +0000 (UTC) Received: from localhost.localdomain (unknown [104.207.83.1]) (using TLSv1.2 with cipher AES128-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id 6E12220452; Fri, 15 May 2015 08:13:08 +0000 (UTC) From: shawnguo@kernel.org To: linux-arm-kernel@lists.infradead.org Subject: [PATCH 6/9] ARM: imx: define gpt register offset per device type Date: Fri, 15 May 2015 16:11:44 +0800 Message-Id: <1431677507-27420-7-git-send-email-shawnguo@kernel.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1431677507-27420-1-git-send-email-shawnguo@kernel.org> References: <1431677507-27420-1-git-send-email-shawnguo@kernel.org> X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00, UNPARSEABLE_RELAY autolearn=ham version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20150515_011332_751787_4046B59E X-CRM114-Status: GOOD ( 14.97 ) X-Spam-Score: -0.0 (/) X-Spam-Report: SpamAssassin version 3.4.0 on bombadil.infradead.org summary: Content analysis details: (-0.0 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 T_RP_MATCHES_RCVD Envelope sender domain matches handover relay domain Cc: Shawn Guo , Daniel Lezcano , kernel@pengutronix.de, Shenwei Wang X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.18-1 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: , List-Help: , List-Subscribe: , MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patch=linaro.org@lists.infradead.org X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: patch@linaro.org X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.215.45 as permitted sender) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 From: Shawn Guo It initializes offset of gpt registers TSTAT, TCN and TCMP per device type, so that the access to these registers can be unified. Signed-off-by: Shawn Guo --- arch/arm/mach-imx/time.c | 31 +++++++++++++++++++------------ 1 file changed, 19 insertions(+), 12 deletions(-) diff --git a/arch/arm/mach-imx/time.c b/arch/arm/mach-imx/time.c index d79a00e24084..5908e78d9552 100644 --- a/arch/arm/mach-imx/time.c +++ b/arch/arm/mach-imx/time.c @@ -91,6 +91,9 @@ struct imx_timer { int irq; struct clk *clk_per; struct clk *clk_ipg; + int reg_tstat; + int reg_tcn; + int reg_tcmp; void (*gpt_setup_tctl)(void); }; @@ -147,7 +150,7 @@ static unsigned long imx_read_current_timer(void) static int __init mxc_clocksource_init(void) { unsigned int c = clk_get_rate(imxtm.clk_per); - void __iomem *reg = imxtm.base + (timer_is_v2() ? V2_TCN : MX1_2_TCN); + void __iomem *reg = imxtm.base + imxtm.reg_tcn; imx_delay_timer.read_current_timer = &imx_read_current_timer; imx_delay_timer.freq = c; @@ -214,13 +217,8 @@ static void mxc_set_mode(enum clock_event_mode mode, gpt_irq_disable(); if (mode != clockevent_mode) { - /* Set event time into far-far future */ - if (timer_is_v2()) - __raw_writel(__raw_readl(imxtm.base + V2_TCN) - 3, - imxtm.base + V2_TCMP); - else - __raw_writel(__raw_readl(imxtm.base + MX1_2_TCN) - 3, - imxtm.base + MX1_2_TCMP); + __raw_writel(__raw_readl(imxtm.base + imxtm.reg_tcn) - 3, + imxtm.base + imxtm.reg_tcmp); /* Clear pending interrupt */ gpt_irq_acknowledge(); @@ -268,10 +266,7 @@ static irqreturn_t mxc_timer_interrupt(int irq, void *dev_id) struct clock_event_device *evt = &clockevent_mxc; uint32_t tstat; - if (timer_is_v2()) - tstat = __raw_readl(imxtm.base + V2_TSTAT); - else - tstat = __raw_readl(imxtm.base + MX1_2_TSTAT); + tstat = __raw_readl(imxtm.base + imxtm.reg_tstat); gpt_irq_acknowledge(); @@ -346,18 +341,30 @@ static void __init imx_timer_data_init(void) { switch (imxtm.type) { case GPT_TYPE_IMX1: + imxtm.reg_tstat = MX1_2_TSTAT; + imxtm.reg_tcn = MX1_2_TCN; + imxtm.reg_tcmp = MX1_2_TCMP; imxtm.gpt_setup_tctl = imx1_gpt_setup_tctl; clockevent_mxc.set_next_event = mx1_2_set_next_event; break; case GPT_TYPE_IMX21: + imxtm.reg_tstat = MX1_2_TSTAT; + imxtm.reg_tcn = MX1_2_TCN; + imxtm.reg_tcmp = MX1_2_TCMP; imxtm.gpt_setup_tctl = imx21_gpt_setup_tctl; clockevent_mxc.set_next_event = mx1_2_set_next_event; break; case GPT_TYPE_IMX31: + imxtm.reg_tstat = V2_TSTAT; + imxtm.reg_tcn = V2_TCN; + imxtm.reg_tcmp = V2_TCMP; imxtm.gpt_setup_tctl = imx31_gpt_setup_tctl; clockevent_mxc.set_next_event = v2_set_next_event; break; case GPT_TYPE_IMX6DL: + imxtm.reg_tstat = V2_TSTAT; + imxtm.reg_tcn = V2_TCN; + imxtm.reg_tcmp = V2_TCMP; imxtm.gpt_setup_tctl = imx6dl_gpt_setup_tctl; clockevent_mxc.set_next_event = v2_set_next_event; break;