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[2001:1868:205::9]) by mx.google.com with ESMTPS id x14si1432581pas.213.2015.05.15.01.16.10 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 15 May 2015 01:16:10 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-arm-kernel-bounces+patch=linaro.org@lists.infradead.org designates 2001:1868:205::9 as permitted sender) client-ip=2001:1868:205::9; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1YtAkw-0006bv-M9; Fri, 15 May 2015 08:14:06 +0000 Received: from mail.kernel.org ([198.145.29.136]) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1YtAk9-0006Fa-G7 for linux-arm-kernel@lists.infradead.org; Fri, 15 May 2015 08:13:18 +0000 Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 2372F203ED; Fri, 15 May 2015 08:12:59 +0000 (UTC) Received: from localhost.localdomain (unknown [104.207.83.1]) (using TLSv1.2 with cipher AES128-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id 6406D20411; Fri, 15 May 2015 08:12:56 +0000 (UTC) From: shawnguo@kernel.org To: linux-arm-kernel@lists.infradead.org Subject: [PATCH 2/9] ARM: imx: define an enum for gpt timer device type Date: Fri, 15 May 2015 16:11:40 +0800 Message-Id: <1431677507-27420-3-git-send-email-shawnguo@kernel.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1431677507-27420-1-git-send-email-shawnguo@kernel.org> References: <1431677507-27420-1-git-send-email-shawnguo@kernel.org> X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00, UNPARSEABLE_RELAY autolearn=ham version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20150515_011317_705485_59EEF25C X-CRM114-Status: GOOD ( 16.15 ) X-Spam-Score: -0.0 (/) X-Spam-Report: SpamAssassin version 3.4.0 on bombadil.infradead.org summary: Content analysis details: (-0.0 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 T_RP_MATCHES_RCVD Envelope sender domain matches handover relay domain Cc: Shawn Guo , Daniel Lezcano , kernel@pengutronix.de, Shenwei Wang X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.18-1 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: , List-Help: , List-Subscribe: , MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patch=linaro.org@lists.infradead.org X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: patch@linaro.org X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.215.51 as permitted sender) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 From: Shawn Guo Define an enum for gpt timer device type in include/soc/imx/timer.h to tell the gpt block differences among SoCs. Update non-DT users (clock drivers) to pass the device type. As we now have include/soc/imx/timer.h, the declaration of mxc_timer_init() is moved into there as the best fit. Signed-off-by: Shawn Guo --- arch/arm/mach-imx/time.c | 6 +++++- drivers/clk/imx/clk-imx1.c | 3 ++- drivers/clk/imx/clk-imx21.c | 3 ++- drivers/clk/imx/clk-imx27.c | 3 ++- drivers/clk/imx/clk-imx31.c | 3 ++- drivers/clk/imx/clk-imx35.c | 3 ++- drivers/clk/imx/clk.h | 7 ------- include/soc/imx/timer.h | 26 ++++++++++++++++++++++++++ 8 files changed, 41 insertions(+), 13 deletions(-) create mode 100644 include/soc/imx/timer.h diff --git a/arch/arm/mach-imx/time.c b/arch/arm/mach-imx/time.c index 8ad7cb2a7f08..5241a173fd60 100644 --- a/arch/arm/mach-imx/time.c +++ b/arch/arm/mach-imx/time.c @@ -31,6 +31,7 @@ #include #include #include +#include #include @@ -85,6 +86,7 @@ static struct clock_event_device clockevent_mxc; static enum clock_event_mode clockevent_mode = CLOCK_EVT_MODE_UNUSED; struct imx_timer { + enum imx_gpt_type type; void __iomem *base; int irq; struct clk *clk_per; @@ -352,7 +354,7 @@ static void __init _mxc_timer_init(void) setup_irq(imxtm.irq, &mxc_timer_irq); } -void __init mxc_timer_init(unsigned long pbase, int irq) +void __init mxc_timer_init(unsigned long pbase, int irq, enum imx_gpt_type type) { imxtm.clk_per = clk_get_sys("imx-gpt.0", "per"); imxtm.clk_ipg = clk_get_sys("imx-gpt.0", "ipg"); @@ -360,6 +362,8 @@ void __init mxc_timer_init(unsigned long pbase, int irq) imxtm.base = ioremap(pbase, SZ_4K); BUG_ON(!imxtm.base); + imxtm.type = type; + _mxc_timer_init(); } diff --git a/drivers/clk/imx/clk-imx1.c b/drivers/clk/imx/clk-imx1.c index c9812dbacac2..c2647fa19f28 100644 --- a/drivers/clk/imx/clk-imx1.c +++ b/drivers/clk/imx/clk-imx1.c @@ -23,6 +23,7 @@ #include #include #include +#include #include #include "clk.h" @@ -102,7 +103,7 @@ int __init mx1_clocks_init(unsigned long fref) clk_register_clkdev(clk[IMX1_CLK_DUMMY], "ipg", "imx1-fb.0"); clk_register_clkdev(clk[IMX1_CLK_DUMMY], "ahb", "imx1-fb.0"); - mxc_timer_init(MX1_TIM1_BASE_ADDR, MX1_TIM1_INT); + mxc_timer_init(MX1_TIM1_BASE_ADDR, MX1_TIM1_INT, GPT_TYPE_IMX1); return 0; } diff --git a/drivers/clk/imx/clk-imx21.c b/drivers/clk/imx/clk-imx21.c index 0ca842cf4ca7..dba987e3b89f 100644 --- a/drivers/clk/imx/clk-imx21.c +++ b/drivers/clk/imx/clk-imx21.c @@ -15,6 +15,7 @@ #include #include #include +#include #include #include "clk.h" @@ -156,7 +157,7 @@ int __init mx21_clocks_init(unsigned long lref, unsigned long href) clk_register_clkdev(clk[IMX21_CLK_I2C_GATE], NULL, "imx21-i2c.0"); clk_register_clkdev(clk[IMX21_CLK_OWIRE_GATE], NULL, "mxc_w1.0"); - mxc_timer_init(MX21_GPT1_BASE_ADDR, MX21_INT_GPT1); + mxc_timer_init(MX21_GPT1_BASE_ADDR, MX21_INT_GPT1, GPT_TYPE_IMX21); return 0; } diff --git a/drivers/clk/imx/clk-imx27.c b/drivers/clk/imx/clk-imx27.c index df2dfc081c71..d9d50d54ef2a 100644 --- a/drivers/clk/imx/clk-imx27.c +++ b/drivers/clk/imx/clk-imx27.c @@ -6,6 +6,7 @@ #include #include #include +#include #include #include "clk.h" @@ -233,7 +234,7 @@ int __init mx27_clocks_init(unsigned long fref) clk_register_clkdev(clk[IMX27_CLK_EMMA_AHB_GATE], "ahb", "m2m-emmaprp.0"); clk_register_clkdev(clk[IMX27_CLK_EMMA_IPG_GATE], "ipg", "m2m-emmaprp.0"); - mxc_timer_init(MX27_GPT1_BASE_ADDR, MX27_INT_GPT1); + mxc_timer_init(MX27_GPT1_BASE_ADDR, MX27_INT_GPT1, GPT_TYPE_IMX21); return 0; } diff --git a/drivers/clk/imx/clk-imx31.c b/drivers/clk/imx/clk-imx31.c index a55290c1c264..fe66c40b7be2 100644 --- a/drivers/clk/imx/clk-imx31.c +++ b/drivers/clk/imx/clk-imx31.c @@ -22,6 +22,7 @@ #include #include #include +#include #include #include "clk.h" @@ -198,7 +199,7 @@ int __init mx31_clocks_init(unsigned long fref) mx31_revision(); clk_disable_unprepare(clk[iim_gate]); - mxc_timer_init(MX31_GPT1_BASE_ADDR, MX31_INT_GPT); + mxc_timer_init(MX31_GPT1_BASE_ADDR, MX31_INT_GPT, GPT_TYPE_IMX31); return 0; } diff --git a/drivers/clk/imx/clk-imx35.c b/drivers/clk/imx/clk-imx35.c index f2f3b8164f7b..69138ba3dec7 100644 --- a/drivers/clk/imx/clk-imx35.c +++ b/drivers/clk/imx/clk-imx35.c @@ -14,6 +14,7 @@ #include #include #include +#include #include #include "clk.h" @@ -293,7 +294,7 @@ int __init mx35_clocks_init(void) imx_print_silicon_rev("i.MX35", mx35_revision()); - mxc_timer_init(MX35_GPT1_BASE_ADDR, MX35_INT_GPT); + mxc_timer_init(MX35_GPT1_BASE_ADDR, MX35_INT_GPT, GPT_TYPE_IMX31); return 0; } diff --git a/drivers/clk/imx/clk.h b/drivers/clk/imx/clk.h index 6bae5374dc83..b5297e457a8e 100644 --- a/drivers/clk/imx/clk.h +++ b/drivers/clk/imx/clk.h @@ -6,13 +6,6 @@ extern spinlock_t imx_ccm_lock; -/* - * This is a stop-gap solution for clock drivers like imx1/imx21 which call - * mxc_timer_init() to initialize timer for non-DT boot. It can be removed - * when these legacy non-DT support is converted or dropped. - */ -void mxc_timer_init(unsigned long pbase, int irq); - void imx_check_clocks(struct clk *clks[], unsigned int count); extern void imx_cscmr1_fixup(u32 *val); diff --git a/include/soc/imx/timer.h b/include/soc/imx/timer.h new file mode 100644 index 000000000000..bbbafd65f464 --- /dev/null +++ b/include/soc/imx/timer.h @@ -0,0 +1,26 @@ +/* + * Copyright 2015 Linaro Ltd. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef __SOC_IMX_TIMER_H__ +#define __SOC_IMX_TIMER_H__ + +enum imx_gpt_type { + GPT_TYPE_IMX1, /* i.MX1 */ + GPT_TYPE_IMX21, /* i.MX21/27 */ + GPT_TYPE_IMX31, /* i.MX31/35/25/37/51/6Q */ + GPT_TYPE_IMX6DL, /* i.MX6DL/SX/SL */ +}; + +/* + * This is a stop-gap solution for clock drivers like imx1/imx21 which call + * mxc_timer_init() to initialize timer for non-DT boot. It can be removed + * when these legacy non-DT support is converted or dropped. + */ +void mxc_timer_init(unsigned long pbase, int irq, enum imx_gpt_type type); + +#endif /* __SOC_IMX_TIMER_H__ */