From patchwork Fri May 15 08:11:39 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Shawn Guo X-Patchwork-Id: 48545 Return-Path: X-Original-To: linaro@patches.linaro.org Delivered-To: linaro@patches.linaro.org Received: from mail-wg0-f71.google.com (mail-wg0-f71.google.com [74.125.82.71]) by ip-10-151-82-157.ec2.internal (Postfix) with ESMTPS id CCD5A21411 for ; Fri, 15 May 2015 08:15:33 +0000 (UTC) Received: by wgin8 with SMTP id n8sf27241707wgi.0 for ; Fri, 15 May 2015 01:15:33 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:delivered-to:from:to:subject:date:message-id :in-reply-to:references:cc:precedence:list-id:list-unsubscribe :list-archive:list-post:list-help:list-subscribe:mime-version :content-type:content-transfer-encoding:sender:errors-to :x-original-sender:x-original-authentication-results:mailing-list; bh=gOg910Kjlk5SPzdJ987OniK4gQStg7QDlscyHoXH6EQ=; b=HWSxoq4V3LXjJ4DcdtvGYNoZ7wsPyINT+yGBXbIRoLYz4k5lzxEdeJVjQt46FGwbr8 86NOhhj1fyfjfbpoWZaXGgNpC3t9vQdfvguBxrbikFrNwP+L4xwGdN16rTcYI1bciVVM OQlAeXzQ6toG4xIR/0zDELtB+AQdckG9ShXpFC2PAklC5vOjNotpay0nV5hoyiTrYVWz JdUv4F4wvIw6jJOXixIcKjp70QToxY3Dj2+Y65gprHvHMq28+8EKscMhOra9C25UV6uR H7stb1Z7XnTmw86rnHngBUljClpULdpN2tWAL/SrU33Eq6uXnxo6mjOjvDClcIFaj0fG daGQ== X-Gm-Message-State: ALoCoQktOwYbyLPkomf2x6Z+jZPdAfTVffdNPVR3XsWkiv/k27F5230gljOUq5cud1kRQ/2x5ZGU X-Received: by 10.113.11.3 with SMTP id ee3mr6105280lbd.9.1431677732788; Fri, 15 May 2015 01:15:32 -0700 (PDT) X-BeenThere: patchwork-forward@linaro.org Received: by 10.152.21.98 with SMTP id u2ls467776lae.84.gmail; Fri, 15 May 2015 01:15:32 -0700 (PDT) X-Received: by 10.152.234.42 with SMTP id ub10mr6221279lac.60.1431677732671; Fri, 15 May 2015 01:15:32 -0700 (PDT) Received: from mail-la0-f48.google.com (mail-la0-f48.google.com. [209.85.215.48]) by mx.google.com with ESMTPS id rm3si598850lbb.5.2015.05.15.01.15.32 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 15 May 2015 01:15:32 -0700 (PDT) Received-SPF: pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.215.48 as permitted sender) client-ip=209.85.215.48; Received: by lagr1 with SMTP id r1so26357282lag.0 for ; Fri, 15 May 2015 01:15:32 -0700 (PDT) X-Received: by 10.112.161.226 with SMTP id xv2mr6420957lbb.106.1431677732564; Fri, 15 May 2015 01:15:32 -0700 (PDT) X-Forwarded-To: patchwork-forward@linaro.org X-Forwarded-For: patch@linaro.org patchwork-forward@linaro.org Delivered-To: patch@linaro.org Received: by 10.112.108.230 with SMTP id hn6csp1830518lbb; Fri, 15 May 2015 01:15:31 -0700 (PDT) X-Received: by 10.66.102.37 with SMTP id fl5mr3760451pab.88.1431677730618; Fri, 15 May 2015 01:15:30 -0700 (PDT) Received: from bombadil.infradead.org (bombadil.infradead.org. [2001:1868:205::9]) by mx.google.com with ESMTPS id h8si1450263pde.174.2015.05.15.01.15.29 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 15 May 2015 01:15:30 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-arm-kernel-bounces+patch=linaro.org@lists.infradead.org designates 2001:1868:205::9 as permitted sender) client-ip=2001:1868:205::9; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1YtAkX-0006T4-W6; Fri, 15 May 2015 08:13:41 +0000 Received: from mail.kernel.org ([198.145.29.136]) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1YtAk4-0006Ee-Tn for linux-arm-kernel@lists.infradead.org; Fri, 15 May 2015 08:13:14 +0000 Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id E8D3A203F7; Fri, 15 May 2015 08:12:55 +0000 (UTC) Received: from localhost.localdomain (unknown [104.207.83.1]) (using TLSv1.2 with cipher AES128-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id 0C423203ED; Fri, 15 May 2015 08:12:51 +0000 (UTC) From: shawnguo@kernel.org To: linux-arm-kernel@lists.infradead.org Subject: [PATCH 1/9] ARM: imx: move timer resources into a structure Date: Fri, 15 May 2015 16:11:39 +0800 Message-Id: <1431677507-27420-2-git-send-email-shawnguo@kernel.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1431677507-27420-1-git-send-email-shawnguo@kernel.org> References: <1431677507-27420-1-git-send-email-shawnguo@kernel.org> X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00, UNPARSEABLE_RELAY autolearn=ham version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20150515_011313_112060_81B243C9 X-CRM114-Status: GOOD ( 21.02 ) X-Spam-Score: -0.0 (/) X-Spam-Report: SpamAssassin version 3.4.0 on bombadil.infradead.org summary: Content analysis details: (-0.0 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 T_RP_MATCHES_RCVD Envelope sender domain matches handover relay domain Cc: Shawn Guo , Daniel Lezcano , kernel@pengutronix.de, Shenwei Wang X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.18-1 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: , List-Help: , List-Subscribe: , MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patch=linaro.org@lists.infradead.org X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: patch@linaro.org X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.215.48 as permitted sender) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 From: Shawn Guo Instead of passing around as argument, let's move timer resources like irq and clocks together with base address into a data structure, and reference the resources from the struct variable directly to simplify the function call interface. Signed-off-by: Shawn Guo --- arch/arm/mach-imx/time.c | 119 ++++++++++++++++++++++++----------------------- 1 file changed, 61 insertions(+), 58 deletions(-) diff --git a/arch/arm/mach-imx/time.c b/arch/arm/mach-imx/time.c index ab5ee1c445f3..8ad7cb2a7f08 100644 --- a/arch/arm/mach-imx/time.c +++ b/arch/arm/mach-imx/time.c @@ -84,27 +84,34 @@ static struct clock_event_device clockevent_mxc; static enum clock_event_mode clockevent_mode = CLOCK_EVT_MODE_UNUSED; -static void __iomem *timer_base; +struct imx_timer { + void __iomem *base; + int irq; + struct clk *clk_per; + struct clk *clk_ipg; +}; + +static struct imx_timer imxtm; static inline void gpt_irq_disable(void) { unsigned int tmp; if (timer_is_v2()) - __raw_writel(0, timer_base + V2_IR); + __raw_writel(0, imxtm.base + V2_IR); else { - tmp = __raw_readl(timer_base + MXC_TCTL); - __raw_writel(tmp & ~MX1_2_TCTL_IRQEN, timer_base + MXC_TCTL); + tmp = __raw_readl(imxtm.base + MXC_TCTL); + __raw_writel(tmp & ~MX1_2_TCTL_IRQEN, imxtm.base + MXC_TCTL); } } static inline void gpt_irq_enable(void) { if (timer_is_v2()) - __raw_writel(1<<0, timer_base + V2_IR); + __raw_writel(1<<0, imxtm.base + V2_IR); else { - __raw_writel(__raw_readl(timer_base + MXC_TCTL) | MX1_2_TCTL_IRQEN, - timer_base + MXC_TCTL); + __raw_writel(__raw_readl(imxtm.base + MXC_TCTL) | MX1_2_TCTL_IRQEN, + imxtm.base + MXC_TCTL); } } @@ -112,12 +119,12 @@ static void gpt_irq_acknowledge(void) { if (timer_is_v1()) { if (cpu_is_mx1()) - __raw_writel(0, timer_base + MX1_2_TSTAT); + __raw_writel(0, imxtm.base + MX1_2_TSTAT); else __raw_writel(MX2_TSTAT_CAPT | MX2_TSTAT_COMP, - timer_base + MX1_2_TSTAT); + imxtm.base + MX1_2_TSTAT); } else if (timer_is_v2()) - __raw_writel(V2_TSTAT_OF1, timer_base + V2_TSTAT); + __raw_writel(V2_TSTAT_OF1, imxtm.base + V2_TSTAT); } static void __iomem *sched_clock_reg; @@ -134,10 +141,10 @@ static unsigned long imx_read_current_timer(void) return __raw_readl(sched_clock_reg); } -static int __init mxc_clocksource_init(struct clk *timer_clk) +static int __init mxc_clocksource_init(void) { - unsigned int c = clk_get_rate(timer_clk); - void __iomem *reg = timer_base + (timer_is_v2() ? V2_TCN : MX1_2_TCN); + unsigned int c = clk_get_rate(imxtm.clk_per); + void __iomem *reg = imxtm.base + (timer_is_v2() ? V2_TCN : MX1_2_TCN); imx_delay_timer.read_current_timer = &imx_read_current_timer; imx_delay_timer.freq = c; @@ -157,11 +164,11 @@ static int mx1_2_set_next_event(unsigned long evt, { unsigned long tcmp; - tcmp = __raw_readl(timer_base + MX1_2_TCN) + evt; + tcmp = __raw_readl(imxtm.base + MX1_2_TCN) + evt; - __raw_writel(tcmp, timer_base + MX1_2_TCMP); + __raw_writel(tcmp, imxtm.base + MX1_2_TCMP); - return (int)(tcmp - __raw_readl(timer_base + MX1_2_TCN)) < 0 ? + return (int)(tcmp - __raw_readl(imxtm.base + MX1_2_TCN)) < 0 ? -ETIME : 0; } @@ -170,12 +177,12 @@ static int v2_set_next_event(unsigned long evt, { unsigned long tcmp; - tcmp = __raw_readl(timer_base + V2_TCN) + evt; + tcmp = __raw_readl(imxtm.base + V2_TCN) + evt; - __raw_writel(tcmp, timer_base + V2_TCMP); + __raw_writel(tcmp, imxtm.base + V2_TCMP); return evt < 0x7fffffff && - (int)(tcmp - __raw_readl(timer_base + V2_TCN)) < 0 ? + (int)(tcmp - __raw_readl(imxtm.base + V2_TCN)) < 0 ? -ETIME : 0; } @@ -206,11 +213,11 @@ static void mxc_set_mode(enum clock_event_mode mode, if (mode != clockevent_mode) { /* Set event time into far-far future */ if (timer_is_v2()) - __raw_writel(__raw_readl(timer_base + V2_TCN) - 3, - timer_base + V2_TCMP); + __raw_writel(__raw_readl(imxtm.base + V2_TCN) - 3, + imxtm.base + V2_TCMP); else - __raw_writel(__raw_readl(timer_base + MX1_2_TCN) - 3, - timer_base + MX1_2_TCMP); + __raw_writel(__raw_readl(imxtm.base + MX1_2_TCN) - 3, + imxtm.base + MX1_2_TCMP); /* Clear pending interrupt */ gpt_irq_acknowledge(); @@ -259,9 +266,9 @@ static irqreturn_t mxc_timer_interrupt(int irq, void *dev_id) uint32_t tstat; if (timer_is_v2()) - tstat = __raw_readl(timer_base + V2_TSTAT); + tstat = __raw_readl(imxtm.base + V2_TSTAT); else - tstat = __raw_readl(timer_base + MX1_2_TSTAT); + tstat = __raw_readl(imxtm.base + MX1_2_TSTAT); gpt_irq_acknowledge(); @@ -284,49 +291,48 @@ static struct clock_event_device clockevent_mxc = { .rating = 200, }; -static int __init mxc_clockevent_init(struct clk *timer_clk) +static int __init mxc_clockevent_init(void) { if (timer_is_v2()) clockevent_mxc.set_next_event = v2_set_next_event; clockevent_mxc.cpumask = cpumask_of(0); clockevents_config_and_register(&clockevent_mxc, - clk_get_rate(timer_clk), + clk_get_rate(imxtm.clk_per), 0xff, 0xfffffffe); return 0; } -static void __init _mxc_timer_init(int irq, - struct clk *clk_per, struct clk *clk_ipg) +static void __init _mxc_timer_init(void) { uint32_t tctl_val; - if (IS_ERR(clk_per)) { + if (IS_ERR(imxtm.clk_per)) { pr_err("i.MX timer: unable to get clk\n"); return; } - if (!IS_ERR(clk_ipg)) - clk_prepare_enable(clk_ipg); + if (!IS_ERR(imxtm.clk_ipg)) + clk_prepare_enable(imxtm.clk_ipg); - clk_prepare_enable(clk_per); + clk_prepare_enable(imxtm.clk_per); /* * Initialise to a known state (all timers off, and timing reset) */ - __raw_writel(0, timer_base + MXC_TCTL); - __raw_writel(0, timer_base + MXC_TPRER); /* see datasheet note */ + __raw_writel(0, imxtm.base + MXC_TCTL); + __raw_writel(0, imxtm.base + MXC_TPRER); /* see datasheet note */ if (timer_is_v2()) { tctl_val = V2_TCTL_FRR | V2_TCTL_WAITEN | MXC_TCTL_TEN; - if (clk_get_rate(clk_per) == V2_TIMER_RATE_OSC_DIV8) { + if (clk_get_rate(imxtm.clk_per) == V2_TIMER_RATE_OSC_DIV8) { tctl_val |= V2_TCTL_CLK_OSC_DIV8; if (cpu_is_imx6dl() || cpu_is_imx6sx()) { /* 24 / 8 = 3 MHz */ __raw_writel(7 << V2_TPRER_PRE24M, - timer_base + MXC_TPRER); + imxtm.base + MXC_TPRER); tctl_val |= V2_TCTL_24MEN; } } else { @@ -336,47 +342,44 @@ static void __init _mxc_timer_init(int irq, tctl_val = MX1_2_TCTL_FRR | MX1_2_TCTL_CLK_PCLK1 | MXC_TCTL_TEN; } - __raw_writel(tctl_val, timer_base + MXC_TCTL); + __raw_writel(tctl_val, imxtm.base + MXC_TCTL); /* init and register the timer to the framework */ - mxc_clocksource_init(clk_per); - mxc_clockevent_init(clk_per); + mxc_clocksource_init(); + mxc_clockevent_init(); /* Make irqs happen */ - setup_irq(irq, &mxc_timer_irq); + setup_irq(imxtm.irq, &mxc_timer_irq); } void __init mxc_timer_init(unsigned long pbase, int irq) { - struct clk *clk_per = clk_get_sys("imx-gpt.0", "per"); - struct clk *clk_ipg = clk_get_sys("imx-gpt.0", "ipg"); + imxtm.clk_per = clk_get_sys("imx-gpt.0", "per"); + imxtm.clk_ipg = clk_get_sys("imx-gpt.0", "ipg"); - timer_base = ioremap(pbase, SZ_4K); - BUG_ON(!timer_base); + imxtm.base = ioremap(pbase, SZ_4K); + BUG_ON(!imxtm.base); - _mxc_timer_init(irq, clk_per, clk_ipg); + _mxc_timer_init(); } static void __init mxc_timer_init_dt(struct device_node *np) { - struct clk *clk_per, *clk_ipg; - int irq; - - if (timer_base) + if (imxtm.base) return; - timer_base = of_iomap(np, 0); - WARN_ON(!timer_base); - irq = irq_of_parse_and_map(np, 0); + imxtm.base = of_iomap(np, 0); + WARN_ON(!imxtm.base); + imxtm.irq = irq_of_parse_and_map(np, 0); - clk_ipg = of_clk_get_by_name(np, "ipg"); + imxtm.clk_ipg = of_clk_get_by_name(np, "ipg"); /* Try osc_per first, and fall back to per otherwise */ - clk_per = of_clk_get_by_name(np, "osc_per"); - if (IS_ERR(clk_per)) - clk_per = of_clk_get_by_name(np, "per"); + imxtm.clk_per = of_clk_get_by_name(np, "osc_per"); + if (IS_ERR(imxtm.clk_per)) + imxtm.clk_per = of_clk_get_by_name(np, "per"); - _mxc_timer_init(irq, clk_per, clk_ipg); + _mxc_timer_init(); } CLOCKSOURCE_OF_DECLARE(mx1_timer, "fsl,imx1-gpt", mxc_timer_init_dt); CLOCKSOURCE_OF_DECLARE(mx25_timer, "fsl,imx25-gpt", mxc_timer_init_dt);