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[209.132.180.67]) by mx.google.com with ESMTP id x16si19081860pbt.145.2015.05.13.09.38.28; Wed, 13 May 2015 09:38:29 -0700 (PDT) Received-SPF: none (google.com: linux-kernel-owner@vger.kernel.org does not designate permitted sender hosts) client-ip=209.132.180.67; Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S934516AbbEMQiX (ORCPT + 28 others); Wed, 13 May 2015 12:38:23 -0400 Received: from mail-pa0-f46.google.com ([209.85.220.46]:34730 "EHLO mail-pa0-f46.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S934118AbbEMQez (ORCPT ); Wed, 13 May 2015 12:34:55 -0400 Received: by pacyx8 with SMTP id yx8so55671408pac.1 for ; Wed, 13 May 2015 09:34:55 -0700 (PDT) X-Received: by 10.66.141.202 with SMTP id rq10mr39703927pab.64.1431534894954; Wed, 13 May 2015 09:34:54 -0700 (PDT) Received: from t430.cg.shawcable.net ([184.64.168.246]) by mx.google.com with ESMTPSA id ue9sm19388667pbc.78.2015.05.13.09.34.53 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 13 May 2015 09:34:53 -0700 (PDT) From: Mathieu Poirier To: gregkh@linuxfoundation.org Cc: linux-arm-kernel@lists.infradead.org, linux-api@vger.kernel.org, linux-kernel@vger.kernel.org, kaixu.xia@linaro.org, zhang.chunyan@linaro.org, mathieu.poirier@linaro.org Subject: [PATCH v4 05/13] coresight-etm4x: Controls pertaining to the ViewInst register Date: Wed, 13 May 2015 10:34:13 -0600 Message-Id: <1431534861-24986-6-git-send-email-mathieu.poirier@linaro.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1431534861-24986-1-git-send-email-mathieu.poirier@linaro.org> References: <1431534861-24986-1-git-send-email-mathieu.poirier@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: list List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: mathieu.poirier@linaro.org X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.215.47 as permitted sender) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , From: Pratik Patel Adding sysfs entries to control the ViewInst register's event selector along with secure and non-secure exception level instruction tracing. Signed-off-by: Pratik Patel Signed-off-by: Mathieu Poirier --- .../ABI/testing/sysfs-bus-coresight-devices-etm4x | 20 +++++ drivers/hwtracing/coresight/coresight-etm4x.c | 98 ++++++++++++++++++++++ 2 files changed, 118 insertions(+) diff --git a/Documentation/ABI/testing/sysfs-bus-coresight-devices-etm4x b/Documentation/ABI/testing/sysfs-bus-coresight-devices-etm4x index 7e5f9bf1d508..ca0a51838e35 100644 --- a/Documentation/ABI/testing/sysfs-bus-coresight-devices-etm4x +++ b/Documentation/ABI/testing/sysfs-bus-coresight-devices-etm4x @@ -134,3 +134,23 @@ KernelVersion: 4.01 Contact: Mathieu Poirier Description: (RW) Controls which regions in the memory map are enabled to use branch broadcasting. + +What: /sys/bus/coresight/devices/.etm/event_vinst +Date: April 2015 +KernelVersion: 4.01 +Contact: Mathieu Poirier +Description: (RW) Controls instruction trace filtering. + +What: /sys/bus/coresight/devices/.etm/s_exlevel_vinst +Date: April 2015 +KernelVersion: 4.01 +Contact: Mathieu Poirier +Description: (RW) In Secure state, each bit controls whether instruction + tracing is enabled for the corresponding exception level. + +What: /sys/bus/coresight/devices/.etm/ns_exlevel_vinst +Date: April 2015 +KernelVersion: 4.01 +Contact: Mathieu Poirier +Description: (RW) In non-secure state, each bit controls whether instruction + tracing is enabled for the corresponding exception level. diff --git a/drivers/hwtracing/coresight/coresight-etm4x.c b/drivers/hwtracing/coresight/coresight-etm4x.c index 51fbda837026..e44cc8464134 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x.c +++ b/drivers/hwtracing/coresight/coresight-etm4x.c @@ -932,6 +932,101 @@ static ssize_t bb_ctrl_store(struct device *dev, } static DEVICE_ATTR_RW(bb_ctrl); +static ssize_t event_vinst_show(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + unsigned long val; + struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent); + + val = drvdata->vinst_ctrl & ETMv4_EVENT_MASK; + return scnprintf(buf, PAGE_SIZE, "%#lx\n", val); +} + +static ssize_t event_vinst_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t size) +{ + unsigned long val; + struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent); + + if (kstrtoul(buf, 16, &val)) + return -EINVAL; + + spin_lock(&drvdata->spinlock); + val &= ETMv4_EVENT_MASK; + drvdata->vinst_ctrl &= ~ETMv4_EVENT_MASK; + drvdata->vinst_ctrl |= val; + spin_unlock(&drvdata->spinlock); + return size; +} +static DEVICE_ATTR_RW(event_vinst); + +static ssize_t s_exlevel_vinst_show(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + unsigned long val; + struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent); + + val = BMVAL(drvdata->vinst_ctrl, 16, 19); + return scnprintf(buf, PAGE_SIZE, "%#lx\n", val); +} + +static ssize_t s_exlevel_vinst_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t size) +{ + unsigned long val; + struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent); + + if (kstrtoul(buf, 16, &val)) + return -EINVAL; + + spin_lock(&drvdata->spinlock); + /* clear all EXLEVEL_S bits (bit[18] is never implemented) */ + drvdata->vinst_ctrl &= ~(BIT(16) | BIT(17) | BIT(19)); + /* enable instruction tracing for corresponding exception level */ + val &= drvdata->s_ex_level; + drvdata->vinst_ctrl |= (val << 16); + spin_unlock(&drvdata->spinlock); + return size; +} +static DEVICE_ATTR_RW(s_exlevel_vinst); + +static ssize_t ns_exlevel_vinst_show(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + unsigned long val; + struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent); + + /* EXLEVEL_NS, bits[23:20] */ + val = BMVAL(drvdata->vinst_ctrl, 20, 23); + return scnprintf(buf, PAGE_SIZE, "%#lx\n", val); +} + +static ssize_t ns_exlevel_vinst_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t size) +{ + unsigned long val; + struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent); + + if (kstrtoul(buf, 16, &val)) + return -EINVAL; + + spin_lock(&drvdata->spinlock); + /* clear EXLEVEL_NS bits (bit[23] is never implemented */ + drvdata->vinst_ctrl &= ~(BIT(20) | BIT(21) | BIT(22)); + /* enable instruction tracing for corresponding exception level */ + val &= drvdata->ns_ex_level; + drvdata->vinst_ctrl |= (val << 20); + spin_unlock(&drvdata->spinlock); + return size; +} +static DEVICE_ATTR_RW(ns_exlevel_vinst); + static ssize_t cpu_show(struct device *dev, struct device_attribute *attr, char *buf) { @@ -963,6 +1058,9 @@ static struct attribute *coresight_etmv4_attrs[] = { &dev_attr_syncfreq.attr, &dev_attr_cyc_threshold.attr, &dev_attr_bb_ctrl.attr, + &dev_attr_event_vinst.attr, + &dev_attr_s_exlevel_vinst.attr, + &dev_attr_ns_exlevel_vinst.attr, &dev_attr_cpu.attr, NULL, };