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[209.132.180.67]) by mx.google.com with ESMTP id os6si24274200pab.195.2015.05.13.09.36.29; Wed, 13 May 2015 09:36:30 -0700 (PDT) Received-SPF: none (google.com: linux-kernel-owner@vger.kernel.org does not designate permitted sender hosts) client-ip=209.132.180.67; Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S934490AbbEMQgY (ORCPT + 28 others); Wed, 13 May 2015 12:36:24 -0400 Received: from mail-pa0-f53.google.com ([209.85.220.53]:33254 "EHLO mail-pa0-f53.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S964929AbbEMQfS (ORCPT ); Wed, 13 May 2015 12:35:18 -0400 Received: by pacwv17 with SMTP id wv17so55795986pac.0 for ; Wed, 13 May 2015 09:35:17 -0700 (PDT) X-Received: by 10.66.192.74 with SMTP id he10mr38535370pac.145.1431534917708; Wed, 13 May 2015 09:35:17 -0700 (PDT) Received: from t430.cg.shawcable.net ([184.64.168.246]) by mx.google.com with ESMTPSA id ue9sm19388667pbc.78.2015.05.13.09.35.16 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 13 May 2015 09:35:16 -0700 (PDT) From: Mathieu Poirier To: gregkh@linuxfoundation.org Cc: linux-arm-kernel@lists.infradead.org, linux-api@vger.kernel.org, linux-kernel@vger.kernel.org, kaixu.xia@linaro.org, zhang.chunyan@linaro.org, mathieu.poirier@linaro.org Subject: [PATCH v4 13/13] coresight-etm4x: Read only access to the tracer's ID registers Date: Wed, 13 May 2015 10:34:21 -0600 Message-Id: <1431534861-24986-14-git-send-email-mathieu.poirier@linaro.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1431534861-24986-1-git-send-email-mathieu.poirier@linaro.org> References: <1431534861-24986-1-git-send-email-mathieu.poirier@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: list List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: mathieu.poirier@linaro.org X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.215.45 as permitted sender) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , ETM ID registers contain valuable information about the capabilities of the implementation and are very useful when configuring the device for various trace scenarios. Signed-off-by: Mathieu Poirier --- .../ABI/testing/sysfs-bus-coresight-devices-etm4x | 90 ++++++++++++++++++++++ drivers/hwtracing/coresight/coresight-etm4x.c | 37 +++++++++ 2 files changed, 127 insertions(+) diff --git a/Documentation/ABI/testing/sysfs-bus-coresight-devices-etm4x b/Documentation/ABI/testing/sysfs-bus-coresight-devices-etm4x index bde788dfd3f7..2fe2e3dae487 100644 --- a/Documentation/ABI/testing/sysfs-bus-coresight-devices-etm4x +++ b/Documentation/ABI/testing/sysfs-bus-coresight-devices-etm4x @@ -358,3 +358,93 @@ KernelVersion: 4.01 Contact: Mathieu Poirier Description: (R) Print the content of the Peripheral ID3 Register (0xFEC). The value is taken directly from the HW. + +What: /sys/bus/coresight/devices/.etm/trcidr/trcidr0 +Date: April 2015 +KernelVersion: 4.01 +Contact: Mathieu Poirier +Description: (R) Returns the tracing capabilities of the trace unit (0x1E0). + The value is taken directly from the HW. + +What: /sys/bus/coresight/devices/.etm/trcidr/trcidr1 +Date: April 2015 +KernelVersion: 4.01 +Contact: Mathieu Poirier +Description: (R) Returns the tracing capabilities of the trace unit (0x1E4). + The value is taken directly from the HW. + +What: /sys/bus/coresight/devices/.etm/trcidr/trcidr2 +Date: April 2015 +KernelVersion: 4.01 +Contact: Mathieu Poirier +Description: (R) Returns the maximum size of the data value, data address, + VMID, context ID and instuction address in the trace unit + (0x1E8). The value is taken directly from the HW. + +What: /sys/bus/coresight/devices/.etm/trcidr/trcidr3 +Date: April 2015 +KernelVersion: 4.01 +Contact: Mathieu Poirier +Description: (R) Returns the value associated with various resources + available to the trace unit. See the Trace Macrocell + architecture specification for more details (0x1E8). + The value is taken directly from the HW. + +What: /sys/bus/coresight/devices/.etm/trcidr/trcidr4 +Date: April 2015 +KernelVersion: 4.01 +Contact: Mathieu Poirier +Description: (R) Returns how many resources the trace unit supports (0x1F0). + The value is taken directly from the HW. + +What: /sys/bus/coresight/devices/.etm/trcidr/trcidr5 +Date: April 2015 +KernelVersion: 4.01 +Contact: Mathieu Poirier +Description: (R) Returns how many resources the trace unit supports (0x1F4). + The value is taken directly from the HW. + +What: /sys/bus/coresight/devices/.etm/trcidr/trcidr8 +Date: April 2015 +KernelVersion: 4.01 +Contact: Mathieu Poirier +Description: (R) Returns the maximum speculation depth of the instruction + trace stream. (0x180). The value is taken directly from the HW. + +What: /sys/bus/coresight/devices/.etm/trcidr/trcidr9 +Date: April 2015 +KernelVersion: 4.01 +Contact: Mathieu Poirier +Description: (R) Returns the number of P0 right-hand keys that the trace unit + can use (0x184). The value is taken directly from the HW. + +What: /sys/bus/coresight/devices/.etm/trcidr/trcidr10 +Date: April 2015 +KernelVersion: 4.01 +Contact: Mathieu Poirier +Description: (R) Returns the number of P1 right-hand keys that the trace unit + can use (0x188). The value is taken directly from the HW. + +What: /sys/bus/coresight/devices/.etm/trcidr/trcidr11 +Date: April 2015 +KernelVersion: 4.01 +Contact: Mathieu Poirier +Description: (R) Returns the number of special P1 right-hand keys that the + trace unit can use (0x18C). The value is taken directly from + the HW. + +What: /sys/bus/coresight/devices/.etm/trcidr/trcidr12 +Date: April 2015 +KernelVersion: 4.01 +Contact: Mathieu Poirier +Description: (R) Returns the number of conditional P1 right-hand keys that + the trace unit can use (0x190). The value is taken directly + from the HW. + +What: /sys/bus/coresight/devices/.etm/trcidr/trcidr13 +Date: April 2015 +KernelVersion: 4.01 +Contact: Mathieu Poirier +Description: (R) Returns the number of special conditional P1 right-hand keys + that the trace unit can use (0x194). The value is taken + directly from the HW. diff --git a/drivers/hwtracing/coresight/coresight-etm4x.c b/drivers/hwtracing/coresight/coresight-etm4x.c index 0568e4413411..f0b50af4fc30 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x.c +++ b/drivers/hwtracing/coresight/coresight-etm4x.c @@ -2238,6 +2238,37 @@ static struct attribute *coresight_etmv4_mgmt_attrs[] = { NULL, }; +coresight_simple_func(trcidr0, TRCIDR0); +coresight_simple_func(trcidr1, TRCIDR1); +coresight_simple_func(trcidr2, TRCIDR2); +coresight_simple_func(trcidr3, TRCIDR3); +coresight_simple_func(trcidr4, TRCIDR4); +coresight_simple_func(trcidr5, TRCIDR5); +/* trcidr[6,7] are reserved */ +coresight_simple_func(trcidr8, TRCIDR8); +coresight_simple_func(trcidr9, TRCIDR9); +coresight_simple_func(trcidr10, TRCIDR10); +coresight_simple_func(trcidr11, TRCIDR11); +coresight_simple_func(trcidr12, TRCIDR12); +coresight_simple_func(trcidr13, TRCIDR13); + +static struct attribute *coresight_etmv4_trcidr_attrs[] = { + &dev_attr_trcidr0.attr, + &dev_attr_trcidr1.attr, + &dev_attr_trcidr2.attr, + &dev_attr_trcidr3.attr, + &dev_attr_trcidr4.attr, + &dev_attr_trcidr5.attr, + /* trcidr[6,7] are reserved */ + &dev_attr_trcidr8.attr, + &dev_attr_trcidr9.attr, + &dev_attr_trcidr10.attr, + &dev_attr_trcidr11.attr, + &dev_attr_trcidr12.attr, + &dev_attr_trcidr13.attr, + NULL, +}; + static const struct attribute_group coresight_etmv4_group = { .attrs = coresight_etmv4_attrs, }; @@ -2247,9 +2278,15 @@ static const struct attribute_group coresight_etmv4_mgmt_group = { .name = "mgmt", }; +static const struct attribute_group coresight_etmv4_trcidr_group = { + .attrs = coresight_etmv4_trcidr_attrs, + .name = "trcidr", +}; + static const struct attribute_group *coresight_etmv4_groups[] = { &coresight_etmv4_group, &coresight_etmv4_mgmt_group, + &coresight_etmv4_trcidr_group, NULL, };