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[2001:1868:205::9]) by mx.google.com with ESMTPS id te6si2957774pbc.185.2015.03.27.06.58.19 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 27 Mar 2015 06:58:20 -0700 (PDT) Received-SPF: none (google.com: linux-arm-kernel-bounces+patch=linaro.org@lists.infradead.org does not designate permitted sender hosts) client-ip=2001:1868:205::9; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1YbUkD-0001pc-8Z; Fri, 27 Mar 2015 13:56:17 +0000 Received: from mail-pd0-f173.google.com ([209.85.192.173]) by bombadil.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1YbUhr-0007ji-VZ for linux-arm-kernel@lists.infradead.org; Fri, 27 Mar 2015 13:53:53 +0000 Received: by pdbop1 with SMTP id op1so97202947pdb.2 for ; Fri, 27 Mar 2015 06:53:31 -0700 (PDT) X-Received: by 10.66.124.164 with SMTP id mj4mr36062587pab.83.1427464410995; Fri, 27 Mar 2015 06:53:30 -0700 (PDT) Received: from localhost.localdomain ([180.150.157.4]) by mx.google.com with ESMTPSA id ks6sm2285210pbc.68.2015.03.27.06.53.26 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 27 Mar 2015 06:53:29 -0700 (PDT) From: Jun Nie To: linux-arm-kernel@lists.infradead.org, mturquette@linaro.org, linux@arm.linux.org.uk, shawn.guo@linaro.org, zte-lt@lists.linaro.org, arnd@arndb.de Subject: [PATCH v2 6/7] ARM: zx: enable SMP and hotplug for zx296702 Date: Fri, 27 Mar 2015 21:52:35 +0800 Message-Id: <1427464356-20112-7-git-send-email-jun.nie@linaro.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1427464356-20112-1-git-send-email-jun.nie@linaro.org> References: <1427464356-20112-1-git-send-email-jun.nie@linaro.org> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20150327_065352_107289_BB44B6EB X-CRM114-Status: GOOD ( 17.42 ) X-Spam-Score: -0.7 (/) X-Spam-Report: SpamAssassin version 3.4.0 on bombadil.infradead.org summary: Content analysis details: (-0.7 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.7 RCVD_IN_DNSWL_LOW RBL: Sender listed at http://www.dnswl.org/, low trust [209.85.192.173 listed in list.dnswl.org] -0.0 SPF_PASS SPF: sender matches SPF record -0.0 RCVD_IN_MSPIKE_H2 RBL: Average reputation (+2) [209.85.192.173 listed in wl.mailspike.net] Cc: Jun Nie X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.18-1 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: , List-Help: , List-Subscribe: , MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patch=linaro.org@lists.infradead.org X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: jun.nie@linaro.org X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.215.53 as permitted sender) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 Bring up the secondary core. Enable hotplug with supporting powering off secondary core. Signed-off-by: Jun Nie --- arch/arm/mach-zx/Makefile | 1 + arch/arm/mach-zx/core.h | 19 +++++ arch/arm/mach-zx/headsmp.S | 32 ++++++++ arch/arm/mach-zx/platsmp.c | 189 +++++++++++++++++++++++++++++++++++++++++++++ 4 files changed, 241 insertions(+) create mode 100644 arch/arm/mach-zx/core.h create mode 100644 arch/arm/mach-zx/headsmp.S create mode 100644 arch/arm/mach-zx/platsmp.c diff --git a/arch/arm/mach-zx/Makefile b/arch/arm/mach-zx/Makefile index 7a541c7..7c2edf6 100644 --- a/arch/arm/mach-zx/Makefile +++ b/arch/arm/mach-zx/Makefile @@ -1 +1,2 @@ obj-$(CONFIG_SOC_ZX296702) += zx296702.o +obj-$(CONFIG_SMP) += headsmp.o platsmp.o diff --git a/arch/arm/mach-zx/core.h b/arch/arm/mach-zx/core.h new file mode 100644 index 0000000..3efe8e0 --- /dev/null +++ b/arch/arm/mach-zx/core.h @@ -0,0 +1,19 @@ +/* + * Copyright 2014 Linaro Ltd. + * Copyright (C) 2014 ZTE Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef __MACH_ZX_CORE_H +#define __MACH_ZX_CORE_H + +extern void zx_resume_jump(void); +extern size_t zx_suspend_iram_sz; +extern unsigned long zx_secondary_startup_pa; + +void zx_secondary_startup(void); + +#endif /* __MACH_ZX_CORE_H */ diff --git a/arch/arm/mach-zx/headsmp.S b/arch/arm/mach-zx/headsmp.S new file mode 100644 index 0000000..c0fece0 --- /dev/null +++ b/arch/arm/mach-zx/headsmp.S @@ -0,0 +1,32 @@ +/* + * Copyright 2014 Linaro Ltd. + * Copyright (C) 2014 ZTE Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include + + .align 3 + +/* It runs from physical address */ +ENTRY(zx_resume_jump) + adr r1, zx_secondary_startup_pa + ldr r0, [r1] + bx r0 +ENDPROC(zx_resume_jump) + +ENTRY(zx_secondary_startup_pa) + .word zx_secondary_startup_pa + +ENTRY(zx_suspend_iram_sz) + .word . - zx_resume_jump +ENDPROC(zx_secondary_startup_pa) + + +ENTRY(zx_secondary_startup) + bl v7_invalidate_l1 + b secondary_startup +ENDPROC(zx_secondary_startup) diff --git a/arch/arm/mach-zx/platsmp.c b/arch/arm/mach-zx/platsmp.c new file mode 100644 index 0000000..a369398 --- /dev/null +++ b/arch/arm/mach-zx/platsmp.c @@ -0,0 +1,189 @@ +/* + * Copyright 2014 Linaro Ltd. + * Copyright (C) 2014 ZTE Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include + +#include "core.h" + +#define AON_SYS_CTRL_RESERVED1 0xa8 + +#define BUS_MATRIX_REMAP_CONFIG 0x00 + +#define PCU_CPU0_CTRL 0x00 +#define PCU_CPU1_CTRL 0x04 +#define PCU_CPU1_ST 0x0c +#define PCU_GLOBAL_CTRL 0x14 +#define PCU_EXPEND_CONTROL 0x34 + +#define ZX_IRAM_BASE 0x00200000 + +static void __iomem *pcu_base; +static void __iomem *matrix_base; +static void __iomem *scu_base; + +void __init zx_smp_prepare_cpus(unsigned int max_cpus) +{ + struct device_node *np; + unsigned long base = 0; + void __iomem *aonsysctrl_base; + void __iomem *sys_iram; + + base = scu_a9_get_base(); + scu_base = ioremap(base, SZ_256); + if (!scu_base) { + pr_err("%s: failed to map scu\n", __func__); + return; + } + + scu_enable(scu_base); + + np = of_find_compatible_node(NULL, NULL, "zte,sysctrl"); + if (!np) { + pr_err("%s: failed to find sysctrl node\n", __func__); + return; + } + + aonsysctrl_base = of_iomap(np, 0); + if (!aonsysctrl_base) { + pr_err("%s: failed to map aonsysctrl\n", __func__); + of_node_put(np); + return; + } + + /* + * Write the address of secondary startup into the + * system-wide flags register. The BootMonitor waits + * until it receives a soft interrupt, and then the + * secondary CPU branches to this address. + */ + __raw_writel(virt_to_phys(zx_secondary_startup), + aonsysctrl_base + AON_SYS_CTRL_RESERVED1); + + iounmap(aonsysctrl_base); + of_node_put(np); + + np = of_find_compatible_node(NULL, NULL, "zte,zx296702-pcu"); + pcu_base = of_iomap(np, 0); + of_node_put(np); + WARN_ON(!pcu_base); + + np = of_find_compatible_node(NULL, NULL, "zte,zx-bus-matrix"); + matrix_base = of_iomap(np, 0); + of_node_put(np); + WARN_ON(!matrix_base); + + /* Map the first 4 KB IRAM for suspend usage */ + sys_iram = __arm_ioremap_exec(ZX_IRAM_BASE, PAGE_SIZE, false); + zx_secondary_startup_pa = virt_to_phys(zx_secondary_startup); + fncpy(sys_iram, &zx_resume_jump, zx_suspend_iram_sz); +} + +static int zx_boot_secondary(unsigned int cpu, struct task_struct *idle) +{ + static bool first_boot = true; + + if (first_boot) { + arch_send_wakeup_ipi_mask(cpumask_of(cpu)); + first_boot = false; + return 0; + } + + /* Swap the base address mapping between IRAM and IROM */ + writel_relaxed(0x1, matrix_base + BUS_MATRIX_REMAP_CONFIG); + + /* Power on CPU1 */ + writel_relaxed(0x0, pcu_base + PCU_CPU1_CTRL); + + /* Wait for power on ack */ + while (readl_relaxed(pcu_base + PCU_CPU1_ST) & 0x4) + cpu_relax(); + + /* Swap back the mapping of IRAM and IROM */ + writel_relaxed(0x0, matrix_base + BUS_MATRIX_REMAP_CONFIG); + + return 0; +} + +#ifdef CONFIG_HOTPLUG_CPU +static inline void cpu_enter_lowpower(void) +{ + unsigned int v; + + asm volatile( + "mcr p15, 0, %1, c7, c5, 0\n" + " mcr p15, 0, %1, c7, c10, 4\n" + /* + * Turn off coherency + */ + " mrc p15, 0, %0, c1, c0, 1\n" + " bic %0, %0, %3\n" + " mcr p15, 0, %0, c1, c0, 1\n" + " mrc p15, 0, %0, c1, c0, 0\n" + " bic %0, %0, %2\n" + " mcr p15, 0, %0, c1, c0, 0\n" + : "=&r" (v) + : "r" (0), "Ir" (CR_C), "Ir" (0x40) + : "cc"); +} + +static int zx_cpu_kill(unsigned int cpu) +{ + unsigned long timeout = jiffies + msecs_to_jiffies(2000); + + writel_relaxed(0x2, pcu_base + PCU_CPU1_CTRL); + + while ((readl_relaxed(pcu_base + PCU_CPU1_ST) & 0x3) != 0x0) { + if (time_after(jiffies, timeout)) { + pr_err("*** cpu1 poweroff timeout\n"); + break; + } + } + return 1; +} + +static void zx_cpu_die(unsigned int cpu) +{ + scu_power_mode(scu_base, SCU_PM_POWEROFF); + cpu_enter_lowpower(); + + while (1) + cpu_do_idle(); +} +#endif + +static void zx_secondary_init(unsigned int cpu) +{ + scu_power_mode(scu_base, SCU_PM_NORMAL); +} + +struct smp_operations zx_smp_ops __initdata = { + .smp_prepare_cpus = zx_smp_prepare_cpus, + .smp_secondary_init = zx_secondary_init, + .smp_boot_secondary = zx_boot_secondary, +#ifdef CONFIG_HOTPLUG_CPU + .cpu_kill = zx_cpu_kill, + .cpu_die = zx_cpu_die, +#endif +}; + +CPU_METHOD_OF_DECLARE(zx_smp, "zte,zx296702-smp", &zx_smp_ops);