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[209.132.180.67]) by mx.google.com with ESMTP id gm2si1507102pbc.22.2015.03.26.04.14.16; Thu, 26 Mar 2015 04:14:17 -0700 (PDT) Received-SPF: none (google.com: devicetree-owner@vger.kernel.org does not designate permitted sender hosts) client-ip=209.132.180.67; Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751928AbbCZLOQ (ORCPT + 5 others); Thu, 26 Mar 2015 07:14:16 -0400 Received: from mail-pd0-f177.google.com ([209.85.192.177]:33402 "EHLO mail-pd0-f177.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751888AbbCZLOP (ORCPT ); Thu, 26 Mar 2015 07:14:15 -0400 Received: by pdnc3 with SMTP id c3so59883092pdn.0 for ; Thu, 26 Mar 2015 04:14:15 -0700 (PDT) X-Received: by 10.70.89.195 with SMTP id bq3mr25912773pdb.138.1427368455049; Thu, 26 Mar 2015 04:14:15 -0700 (PDT) Received: from localhost.localdomain ([211.79.119.21]) by mx.google.com with ESMTPSA id wg9sm1875069pab.17.2015.03.26.04.14.10 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 26 Mar 2015 04:14:14 -0700 (PDT) From: Leo Yan To: Wei Xu , Dan Zhao , zhenwei.wang@hisilicon.com, Haojian Zhuang , Bintian Wang , mturquette@linaro.org, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org Cc: Leo Yan Subject: [PATCH 1/4] clk: hisi: add API for allocation clk data struct Date: Thu, 26 Mar 2015 19:13:36 +0800 Message-Id: <1427368419-22222-2-git-send-email-leo.yan@linaro.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1427368419-22222-1-git-send-email-leo.yan@linaro.org> References: <1427368419-22222-1-git-send-email-leo.yan@linaro.org> Sender: devicetree-owner@vger.kernel.org Precedence: list List-ID: X-Mailing-List: devicetree@vger.kernel.org X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: leo.yan@linaro.org X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.217.173 as permitted sender) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , In the old clk init function, it will read the register base address from dts and allocate the clk data structures. But for the some cases, the clock driver don't need init the reg's base address, which will directly access mmio region with syscon. So for clock's initialization, this patch adds one more API which is only for allocating clock data structure. Signed-off-by: Leo Yan --- drivers/clk/hisilicon/clk.c | 42 +++++++++++++++++++++++++++--------------- drivers/clk/hisilicon/clk.h | 2 ++ 2 files changed, 29 insertions(+), 15 deletions(-) diff --git a/drivers/clk/hisilicon/clk.c b/drivers/clk/hisilicon/clk.c index a078e84..1e4c5c6 100644 --- a/drivers/clk/hisilicon/clk.c +++ b/drivers/clk/hisilicon/clk.c @@ -38,30 +38,17 @@ static DEFINE_SPINLOCK(hisi_clk_lock); -struct hisi_clock_data __init *hisi_clk_init(struct device_node *np, - int nr_clks) +struct hisi_clock_data __init *hisi_clk_alloc_data(struct device_node *np, + int nr_clks) { struct hisi_clock_data *clk_data; struct clk **clk_table; - void __iomem *base; - - if (np) { - base = of_iomap(np, 0); - if (!base) { - pr_err("failed to map Hisilicon clock registers\n"); - goto err; - } - } else { - pr_err("failed to find Hisilicon clock node in DTS\n"); - goto err; - } clk_data = kzalloc(sizeof(*clk_data), GFP_KERNEL); if (!clk_data) { pr_err("%s: could not allocate clock data\n", __func__); goto err; } - clk_data->base = base; clk_table = kzalloc(sizeof(struct clk *) * nr_clks, GFP_KERNEL); if (!clk_table) { @@ -72,12 +59,37 @@ struct hisi_clock_data __init *hisi_clk_init(struct device_node *np, clk_data->clk_data.clk_num = nr_clks; of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data->clk_data); return clk_data; + err_data: kfree(clk_data); err: return NULL; } +struct hisi_clock_data __init *hisi_clk_init(struct device_node *np, + int nr_clks) +{ + struct hisi_clock_data *clk_data; + void __iomem *base; + + if (np) { + base = of_iomap(np, 0); + if (!base) { + pr_err("failed to map Hisilicon clock registers\n"); + return NULL; + } + printk("%s: base %p\n", __func__, base); + } else { + pr_err("failed to find Hisilicon clock node in DTS\n"); + return NULL; + } + + clk_data = hisi_clk_alloc_data(np, nr_clks); + if (clk_data) + clk_data->base = base; + return clk_data; +} + void __init hisi_clk_register_fixed_rate(struct hisi_fixed_rate_clock *clks, int nums, struct hisi_clock_data *data) { diff --git a/drivers/clk/hisilicon/clk.h b/drivers/clk/hisilicon/clk.h index 31083ff..624f608 100644 --- a/drivers/clk/hisilicon/clk.h +++ b/drivers/clk/hisilicon/clk.h @@ -96,6 +96,8 @@ struct clk *hisi_register_clkgate_sep(struct device *, const char *, u8, spinlock_t *); struct hisi_clock_data __init *hisi_clk_init(struct device_node *, int); +struct hisi_clock_data __init *hisi_clk_alloc_data(struct device_node *np, + int nr_clks); void __init hisi_clk_register_fixed_rate(struct hisi_fixed_rate_clock *, int, struct hisi_clock_data *); void __init hisi_clk_register_fixed_factor(struct hisi_fixed_factor_clock *,