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[62.82.106.185]) by mx.google.com with ESMTPSA id s5sm11712061wia.1.2015.03.23.08.37.07 (version=TLSv1.1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Mon, 23 Mar 2015 08:37:07 -0700 (PDT) From: Ard Biesheuvel To: linux-arm-kernel@lists.infradead.org, mark.rutland@arm.com, will.deacon@arm.com, catalin.marinas@arm.com Subject: [PATCH 4/4] arm64: align PHYS_OFFSET to block size Date: Mon, 23 Mar 2015 16:36:56 +0100 Message-Id: <1427125016-3873-5-git-send-email-ard.biesheuvel@linaro.org> X-Mailer: git-send-email 1.8.3.2 In-Reply-To: <1427125016-3873-1-git-send-email-ard.biesheuvel@linaro.org> References: <1427125016-3873-1-git-send-email-ard.biesheuvel@linaro.org> In-Reply-To: <20150317164353.GN23340@leverpostej> References: <20150317164353.GN23340@leverpostej> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20150323_083730_434111_C0679B2B X-CRM114-Status: UNSURE ( 8.76 ) X-CRM114-Notice: Please train this message. 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X-Original-Sender: ard.biesheuvel@linaro.org X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.217.171 as permitted sender) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 This aligns PHYS_OFFSET down to an alignment that allows system RAM to be mapped using the largest blocks available, i.e., 1 GB blocks on 4 KB pages or 512 MB blocks on 64 KB pages. Signed-off-by: Ard Biesheuvel --- arch/arm64/kernel/head.S | 11 ++++++++--- 1 file changed, 8 insertions(+), 3 deletions(-) diff --git a/arch/arm64/kernel/head.S b/arch/arm64/kernel/head.S index 16134608eecf..fd8434753372 100644 --- a/arch/arm64/kernel/head.S +++ b/arch/arm64/kernel/head.S @@ -49,13 +49,15 @@ #ifdef CONFIG_ARM64_64K_PAGES #define BLOCK_SHIFT PAGE_SHIFT #define BLOCK_SIZE PAGE_SIZE -#define TABLE_SHIFT PMD_SHIFT #else #define BLOCK_SHIFT SECTION_SHIFT #define BLOCK_SIZE SECTION_SIZE -#define TABLE_SHIFT PUD_SHIFT #endif +#define TABLE_SHIFT (BLOCK_SHIFT + PAGE_SHIFT - 3) +#define TABLE_SIZE (1 << TABLE_SHIFT) +#define TABLE_MASK (~(TABLE_SIZE - 1)) + #define KERNEL_START _text #define KERNEL_END _end @@ -237,7 +239,10 @@ ENTRY(stext) bl el2_setup // Drop to EL1, w20=cpu_boot_mode adrp x24, __PHYS_OFFSET - mov x23, #KIMAGE_OFFSET + and x23, x24, #~TABLE_MASK // image offset + and x24, x24, #TABLE_MASK // PHYS_OFFSET + mov x0, #KIMAGE_OFFSET + add x23, x23, x0 bl set_cpu_boot_mode_flag bl __create_page_tables // x25=TTBR0, x26=TTBR1