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[2001:1868:205::9]) by mx.google.com with ESMTPS id bu12si36777293pdb.92.2015.03.18.08.43.30 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 18 Mar 2015 08:43:31 -0700 (PDT) Received-SPF: none (google.com: linux-arm-kernel-bounces+patch=linaro.org@lists.infradead.org does not designate permitted sender hosts) client-ip=2001:1868:205::9; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1YYG6B-00083F-4y; Wed, 18 Mar 2015 15:41:35 +0000 Received: from mail-wg0-f54.google.com ([74.125.82.54]) by bombadil.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1YYFOL-0003bc-3p for linux-arm-kernel@lists.infradead.org; Wed, 18 Mar 2015 14:56:18 +0000 Received: by wgdm6 with SMTP id m6so37543380wgd.2 for ; Wed, 18 Mar 2015 07:55:54 -0700 (PDT) X-Received: by 10.194.60.77 with SMTP id f13mr144880008wjr.105.1426690554719; Wed, 18 Mar 2015 07:55:54 -0700 (PDT) Received: from ards-macbook-pro.local ([84.78.25.113]) by mx.google.com with ESMTPSA id y14sm24826582wjr.39.2015.03.18.07.55.52 (version=TLSv1.1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Wed, 18 Mar 2015 07:55:54 -0700 (PDT) From: Ard Biesheuvel To: will.deacon@arm.com, mark.rutland@arm.com, catalin.marinas@arm.com, linux-arm-kernel@lists.infradead.org Subject: [PATCH v5 8/8] arm64: enforce x1|x2|x3 == 0 upon kernel entry as per boot protocol Date: Wed, 18 Mar 2015 15:55:27 +0100 Message-Id: <1426690527-14258-9-git-send-email-ard.biesheuvel@linaro.org> X-Mailer: git-send-email 1.8.3.2 In-Reply-To: <1426690527-14258-1-git-send-email-ard.biesheuvel@linaro.org> References: <1426690527-14258-1-git-send-email-ard.biesheuvel@linaro.org> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20150318_075617_347354_97EC114C X-CRM114-Status: GOOD ( 11.41 ) X-Spam-Score: -0.7 (/) X-Spam-Report: SpamAssassin version 3.4.0 on bombadil.infradead.org summary: Content analysis details: (-0.7 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 RCVD_IN_MSPIKE_H3 RBL: Good reputation (+3) [74.125.82.54 listed in wl.mailspike.net] -0.7 RCVD_IN_DNSWL_LOW RBL: Sender listed at http://www.dnswl.org/, low trust [74.125.82.54 listed in list.dnswl.org] -0.0 SPF_PASS SPF: sender matches SPF record -0.0 RCVD_IN_MSPIKE_WL Mailspike good senders Cc: marc.zyngier@arm.com, Ard Biesheuvel X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.18-1 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: , List-Help: , List-Subscribe: , MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patch=linaro.org@lists.infradead.org X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: ard.biesheuvel@linaro.org X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.217.175 as permitted sender) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 According to the arm64 boot protocol, registers x1 to x3 should be zero upon kernel entry, and non-zero values are reserved for future use. This future use is going to be problematic if we never enforce the current rules, so start enforcing them now, by emitting a warning if non-zero values are detected. Signed-off-by: Ard Biesheuvel --- arch/arm64/kernel/head.S | 4 ++++ arch/arm64/kernel/setup.c | 15 +++++++++++++++ 2 files changed, 19 insertions(+) diff --git a/arch/arm64/kernel/head.S b/arch/arm64/kernel/head.S index a0fbd99efb89..8636c3cef006 100644 --- a/arch/arm64/kernel/head.S +++ b/arch/arm64/kernel/head.S @@ -233,6 +233,10 @@ section_table: #endif ENTRY(stext) + adr_l x8, boot_regs // record the contents of + stp x0, x1, [x8] // x0 .. x3 at kernel entry + stp x2, x3, [x8, #16] + mov x21, x0 // x21=FDT bl el2_setup // Drop to EL1, w20=cpu_boot_mode adrp x24, __PHYS_OFFSET diff --git a/arch/arm64/kernel/setup.c b/arch/arm64/kernel/setup.c index 6c5fb5aff325..2d5cae2de679 100644 --- a/arch/arm64/kernel/setup.c +++ b/arch/arm64/kernel/setup.c @@ -114,6 +114,11 @@ void __init early_print(const char *str, ...) printk("%s", buf); } +/* + * The recorded values of x0 .. x3 upon kernel entry. + */ +u64 __read_mostly boot_regs[4]; + void __init smp_setup_processor_id(void) { u64 mpidr = read_cpuid_mpidr() & MPIDR_HWID_BITMASK; @@ -387,6 +392,16 @@ void __init setup_arch(char **cmdline_p) conswitchp = &dummy_con; #endif #endif + /* + * boot_regs[] is written by the boot CPU with the caches off, so we + * need to ensure that we read the value from main memory + */ + __flush_dcache_area(boot_regs, sizeof(boot_regs)); + if (boot_regs[1] || boot_regs[2] || boot_regs[3]) { + pr_err("WARNING: boot protocol violation detected (x1 == %llx, x2 == %llx, x3 == %llx)\n", + boot_regs[1], boot_regs[2], boot_regs[3]); + pr_err("WARNING: your bootloader may fail to load newer kernels\n"); + } } static int __init arm64_device_init(void)