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[2001:1868:205::9]) by mx.google.com with ESMTPS id sw9si9405820pab.235.2015.03.14.04.55.00 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sat, 14 Mar 2015 04:55:01 -0700 (PDT) Received-SPF: none (google.com: linux-arm-kernel-bounces+patch=linaro.org@lists.infradead.org does not designate permitted sender hosts) client-ip=2001:1868:205::9; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1YWkd4-00050d-Rd; Sat, 14 Mar 2015 11:53:18 +0000 Received: from mail-pa0-f52.google.com ([209.85.220.52]) by bombadil.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1YWkar-0003CO-3R for linux-arm-kernel@lists.infradead.org; Sat, 14 Mar 2015 11:51:02 +0000 Received: by pagr17 with SMTP id r17so14753071pag.0 for ; Sat, 14 Mar 2015 04:50:39 -0700 (PDT) X-Received: by 10.67.10.47 with SMTP id dx15mr114688372pad.139.1426333839780; Sat, 14 Mar 2015 04:50:39 -0700 (PDT) Received: from localhost.localdomain ([107.6.112.156]) by mx.google.com with ESMTPSA id ov5sm7365488pdb.91.2015.03.14.04.50.35 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Sat, 14 Mar 2015 04:50:38 -0700 (PDT) From: Jun Nie To: linux-arm-kernel@lists.infradead.org, mturquette@linaro.org, linux@arm.linux.org.uk, shawn.guo@linaro.org, jun.nie@linaro.org, zte-lt@lists.linaro.org Subject: [PATCH 08/10] ARM: dts: zx: add an initial dts for zx296702 Date: Sat, 14 Mar 2015 19:49:43 +0800 Message-Id: <1426333785-3952-9-git-send-email-jun.nie@linaro.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1426333785-3952-1-git-send-email-jun.nie@linaro.org> References: <1426333785-3952-1-git-send-email-jun.nie@linaro.org> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20150314_045101_202480_AA9E2B75 X-CRM114-Status: GOOD ( 10.18 ) X-Spam-Score: -0.7 (/) X-Spam-Report: SpamAssassin version 3.4.0 on bombadil.infradead.org summary: Content analysis details: (-0.7 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.7 RCVD_IN_DNSWL_LOW RBL: Sender listed at http://www.dnswl.org/, low trust [209.85.220.52 listed in list.dnswl.org] -0.0 RCVD_IN_MSPIKE_H3 RBL: Good reputation (+3) [209.85.220.52 listed in wl.mailspike.net] -0.0 SPF_PASS SPF: sender matches SPF record -0.0 RCVD_IN_MSPIKE_WL Mailspike good senders X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.18-1 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: , List-Help: , List-Subscribe: , MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patch=linaro.org@lists.infradead.org X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: jun.nie@linaro.org X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.217.171 as permitted sender) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 Add initial dts file for ZX296702 and board ZX296702-AD1. More peripherals will be added later. Signed-off-by: Shawn Guo Signed-off-by: Jun Nie --- arch/arm/boot/dts/Makefile | 1 + arch/arm/boot/dts/zx296702-ad1.dts | 43 +++++++++++++ arch/arm/boot/dts/zx296702.dtsi | 127 +++++++++++++++++++++++++++++++++++++ 3 files changed, 171 insertions(+) create mode 100644 arch/arm/boot/dts/zx296702-ad1.dts create mode 100644 arch/arm/boot/dts/zx296702.dtsi diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index a1c776b..55dcfbc 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -645,6 +645,7 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += \ mt6592-evb.dtb \ mt8127-moose.dtb \ mt8135-evbp1.dtb +dtb-$(CONFIG_ARCH_ZX) += zx296702-ad1.dtb endif always := $(dtb-y) diff --git a/arch/arm/boot/dts/zx296702-ad1.dts b/arch/arm/boot/dts/zx296702-ad1.dts new file mode 100644 index 0000000..cac207a --- /dev/null +++ b/arch/arm/boot/dts/zx296702-ad1.dts @@ -0,0 +1,43 @@ + +/dts-v1/; + +#include "zx296702.dtsi" + +/ { + model = "ZTE ZX296702 AD1 Board"; + compatible = "zte,zx296702-ad1", "zte,zx296702"; + + memory { + reg = <0x50000000 0x20000000>; + }; +}; + +&dwmmc0 { + num-slots = <1>; + supports-highspeed; + non-removable; + disable-wp; + status = "okay"; + + slot@0 { + reg = <0>; + bus-width = <4>; + }; +}; + +&dwmmc1 { + num-slots = <1>; + supports-highspeed; + non-removable; + disable-wp; + status = "okay"; + + slot@0 { + reg = <0>; + bus-width = <8>; + }; +}; + +&uart0 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/zx296702.dtsi b/arch/arm/boot/dts/zx296702.dtsi new file mode 100644 index 0000000..2e66345 --- /dev/null +++ b/arch/arm/boot/dts/zx296702.dtsi @@ -0,0 +1,127 @@ + +#include "skeleton.dtsi" +#include +#include + +/ { + aliases { + serial0 = &uart0; + serial1 = &uart1; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + compatible = "arm,cortex-a9"; + device_type = "cpu"; + reg = <0>; + }; + + cpu@1 { + compatible = "arm,cortex-a9"; + device_type = "cpu"; + reg = <1>; + }; + }; + + + soc { + #address-cells = <1>; + #size-cells = <1>; + compatible = "simple-bus"; + interrupt-parent = <&intc>; + ranges; + + intc: interrupt-controller@00801000 { + compatible = "arm,cortex-a9-gic"; + #interrupt-cells = <3>; + #address-cells = <1>; + #size-cells = <1>; + interrupt-controller; + reg = <0x00801000 0x1000>, + <0x00800100 0x100>; + }; + + global_timer: timer@008000200 { + compatible = "arm,cortex-a9-global-timer"; + reg = <0x00800200 0x20>; + interrupts = ; + interrupt-parent = <&intc>; + clocks = <&clks ZX296702_A9_PERIPHCLK>; + }; + + l2cc: cache-controller@0x00c00000 { + compatible = "arm,pl310-cache"; + reg = <0x00c00000 0x1000>; + arm,data-latency = <1 1 1>; + arm,tag-latency = <1 1 1>; + cache-unified; + cache-level = <2>; + }; + + lsp1crpm: lsp1crpm@0x09400000 { + compatible = "zte,zx296702-lsp1crpm"; + reg = <0x09400000 0x1000>; + }; + + uart0: serial@0x09405000 { + compatible = "zte,zx296702-uart"; + reg = <0x09405000 0x1000>; + interrupts = ; + clocks = <&clks ZX296702_UART0_PCLK>; + status = "disabled"; + }; + + uart1: serial@0x09406000 { + compatible = "zte,zx296702-uart"; + reg = <0x09406000 0x1000>; + interrupts = ; + clocks = <&clks ZX296702_UART1_WCLK>; + status = "disabled"; + }; + + dwmmc0: dwmmc@0x09408000 { + compatible = "snps,dw-mshc"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x09408000 0x1000>; + interrupts = ; + fifo-depth = <32>; + clocks = <&clks ZX296702_SDMMC0_PCLK>, + <&clks ZX296702_SDMMC0_WCLK>; + clock-names = "biu", "ciu"; + status = "disabled"; + }; + + clks: topcrm@0x09800000 { + compatible = "zte,zx296702-topcrm"; + reg = <0x09800000 0x1000>; + #clock-cells = <1>; + }; + + lsp0crpm: lsp0crpm@0x0b000000 { + compatible = "zte,zx296702-lsp0crpm"; + reg = <0x0b000000 0x1000>; + }; + + dwmmc1: dwmmc@0x0b003000 { + compatible = "snps,dw-mshc"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0b003000 0x1000>; + interrupts = ; + fifo-depth = <32>; + clocks = <&clks ZX296702_SDMMC1_PCLK>, + <&clks ZX296702_SDMMC1_WCLK>; + clock-names = "biu", "ciu"; + status = "disabled"; + }; + + aon_sysctrl: aon-sysctrl@0xa0007000 { + compatible = "zte,aon-sysctrl"; + reg = <0xa0007000 0x1000>; + }; + }; +};