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[79.151.58.53]) by mx.google.com with ESMTPSA id w4sm2507612wib.19.2015.03.13.05.07.49 (version=TLSv1.1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Fri, 13 Mar 2015 05:07:51 -0700 (PDT) From: Ard Biesheuvel To: linux-arm-kernel@lists.infradead.org, arnd@arndb.de, linux@arm.linux.org.uk, nico@linaro.org Subject: [PATCH v2 3/8] ARM: add macro to perform far branches (b/bl) Date: Fri, 13 Mar 2015 13:07:27 +0100 Message-Id: <1426248452-4773-4-git-send-email-ard.biesheuvel@linaro.org> X-Mailer: git-send-email 1.8.3.2 In-Reply-To: <1426248452-4773-1-git-send-email-ard.biesheuvel@linaro.org> References: <1426248452-4773-1-git-send-email-ard.biesheuvel@linaro.org> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20150313_050816_411039_5FF3551A X-CRM114-Status: GOOD ( 11.84 ) X-Spam-Score: -0.7 (/) X-Spam-Report: SpamAssassin version 3.4.0 on bombadil.infradead.org summary: Content analysis details: (-0.7 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.7 RCVD_IN_DNSWL_LOW RBL: Sender listed at http://www.dnswl.org/, low trust [74.125.82.51 listed in list.dnswl.org] -0.0 RCVD_IN_MSPIKE_H3 RBL: Good reputation (+3) [74.125.82.51 listed in wl.mailspike.net] -0.0 SPF_PASS SPF: sender matches SPF record -0.0 RCVD_IN_MSPIKE_WL Mailspike good senders Cc: Ard Biesheuvel X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.18-1 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: , List-Help: , List-Subscribe: , MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patch=linaro.org@lists.infradead.org X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: ard.biesheuvel@linaro.org X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.217.178 as permitted sender) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 These macros execute PC-relative branches, but with a larger reach than the 24 bits that are available in the b and bl opcodes. Acked-by: Nicolas Pitre Signed-off-by: Ard Biesheuvel --- arch/arm/include/asm/assembler.h | 83 ++++++++++++++++++++++++++++++++++++++++ 1 file changed, 83 insertions(+) diff --git a/arch/arm/include/asm/assembler.h b/arch/arm/include/asm/assembler.h index f67fd3afebdf..2e7f55194782 100644 --- a/arch/arm/include/asm/assembler.h +++ b/arch/arm/include/asm/assembler.h @@ -88,6 +88,17 @@ #endif /* + * The program counter is always ahead of the address of the currently + * executing instruction by PC_BIAS bytes, whose value differs depending + * on the execution mode. + */ +#ifdef CONFIG_THUMB2_KERNEL +#define PC_BIAS 4 +#else +#define PC_BIAS 8 +#endif + +/* * Enable and disable interrupts */ #if __LINUX_ARM_ARCH__ >= 6 @@ -108,6 +119,78 @@ .endm #endif + /* + * Macros to emit relative conditional branches that may exceed the + * range of the 24-bit immediate of the ordinary b/bl instructions. + * NOTE: this doesn't work with locally defined symbols, as they + * lack the ARM/Thumb annotation (even if they are annotated as + * functions) + */ + .macro b_far, target, tmpreg, c= +#if defined(CONFIG_CPU_32v7) || defined(CONFIG_CPU_32v7M) + movt\c \tmpreg, #:upper16:(\target - (8888f + PC_BIAS)) + movw\c \tmpreg, #:lower16:(\target - (8888f + PC_BIAS)) +8888: add\c pc, pc, \tmpreg +#else + ldr\c \tmpreg, 8889f +8888: add\c pc, pc, \tmpreg + .ifnb \c + b 8890f + .endif +8889: .long \target - (8888b + PC_BIAS) +8890: +#endif + .endm + + .macro bl_far, target, c= +#if defined(CONFIG_CPU_32v7) || defined(CONFIG_CPU_32v7M) + movt\c ip, #:upper16:(\target - (8887f + PC_BIAS)) + movw\c ip, #:lower16:(\target - (8887f + PC_BIAS)) +8887: add\c ip, ip, pc + blx\c ip +#else + adr\c lr, 8887f + b_far \target, ip, \c +8887: +#endif + .endm + + /* + * Macros to emit absolute conditional branches: these are preferred + * over the far variants above because they use fewer instructions + * and/or use implicit literals that the assembler can group together + * to optimize cache utilization. However, they can only be used to + * call functions at their link time address, which rules out early boot + * code that executes with the MMU off. + * The v7 variant uses a movt/movw pair to prevent potential D-cache + * stalls on the literal, so using these macros is preferred over using + * 'ldr pc, =XXX' directly (unless no scratch register is available) + * NOTE: this doesn't work with locally defined symbols, as they + * lack the ARM/Thumb annotation (even if they are annotated as + * functions) + */ + .macro b_abs, target, tmpreg, c= +#if defined(CONFIG_CPU_32v7) || defined(CONFIG_CPU_32v7M) + movt\c \tmpreg, #:upper16:\target + movw\c \tmpreg, #:lower16:\target + bx\c \tmpreg +#else + ldr\c pc, =\target +#endif + .endm + + .macro bl_abs, target, c= +#if defined(CONFIG_CPU_32v7) || defined(CONFIG_CPU_32v7M) + movt\c lr, #:upper16:\target + movw\c lr, #:lower16:\target + blx\c lr +#else + adr\c lr, BSYM(8886f) + ldr\c pc, =\target +8886: +#endif + .endm + .macro asm_trace_hardirqs_off #if defined(CONFIG_TRACE_IRQFLAGS) stmdb sp!, {r0-r3, ip, lr}