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[83.50.109.45]) by mx.google.com with ESMTPSA id m9sm14081659wiz.24.2015.03.12.10.38.38 (version=TLSv1.1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Thu, 12 Mar 2015 10:38:39 -0700 (PDT) From: Ard Biesheuvel To: linux-arm-kernel@lists.infradead.org, arnd@arndb.de, linux@arm.linux.org.uk, nico@linaro.org Subject: [RFT/RFC PATCH 3/6] ARM: add macro to perform far branches (b/bl) Date: Thu, 12 Mar 2015 18:38:09 +0100 Message-Id: <1426181892-15440-4-git-send-email-ard.biesheuvel@linaro.org> X-Mailer: git-send-email 1.8.3.2 In-Reply-To: <1426181892-15440-1-git-send-email-ard.biesheuvel@linaro.org> References: <1426181892-15440-1-git-send-email-ard.biesheuvel@linaro.org> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20150312_103904_456017_C0E00D70 X-CRM114-Status: GOOD ( 10.13 ) X-Spam-Score: -0.7 (/) X-Spam-Report: SpamAssassin version 3.4.0 on bombadil.infradead.org summary: Content analysis details: (-0.7 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.7 RCVD_IN_DNSWL_LOW RBL: Sender listed at http://www.dnswl.org/, low trust [74.125.82.180 listed in list.dnswl.org] -0.0 RCVD_IN_MSPIKE_H3 RBL: Good reputation (+3) [74.125.82.180 listed in wl.mailspike.net] -0.0 SPF_PASS SPF: sender matches SPF record -0.0 RCVD_IN_MSPIKE_WL Mailspike good senders Cc: Ard Biesheuvel X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.18-1 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: , List-Help: , List-Subscribe: , MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patch=linaro.org@lists.infradead.org X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: ard.biesheuvel@linaro.org X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.217.170 as permitted sender) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 These macros execute PC-relative branches, but with a larger reach than the 24 bits that are available in the b and bl opcodes. Signed-off-by: Ard Biesheuvel --- arch/arm/include/asm/assembler.h | 29 +++++++++++++++++++++++++++++ 1 file changed, 29 insertions(+) diff --git a/arch/arm/include/asm/assembler.h b/arch/arm/include/asm/assembler.h index f67fd3afebdf..bd08c3c1b73f 100644 --- a/arch/arm/include/asm/assembler.h +++ b/arch/arm/include/asm/assembler.h @@ -108,6 +108,35 @@ .endm #endif + /* + * Macros to emit relative branches that may exceed the range + * of the 24-bit immediate of the ordinary b/bl instructions. + * NOTE: this doesn't work with locally defined symbols, as they + * might lack the ARM/Thumb annotation (even if they are annotated + * as functions) + */ + .macro b_far, target, tmpreg +#if defined(CONFIG_CPU_32v7) || defined(CONFIG_CPU_32v7M) + ARM( movt \tmpreg, #:upper16:(\target - (8888f + 8)) ) + ARM( movw \tmpreg, #:lower16:(\target - (8888f + 8)) ) + THUMB( movt \tmpreg, #:upper16:(\target - (8888f + 4)) ) + THUMB( movw \tmpreg, #:lower16:(\target - (8888f + 4)) ) +8888: add pc, pc, \tmpreg +#else + ldr \tmpreg, 8889f +8888: add pc, pc, \tmpreg + .align 2 +8889: + ARM( .word \target - (8888b + 8) ) +#endif + .endm + + .macro bl_far, target, tmpreg=ip + adr lr, 8887f + b_far \target, \tmpreg +8887: + .endm + .macro asm_trace_hardirqs_off #if defined(CONFIG_TRACE_IRQFLAGS) stmdb sp!, {r0-r3, ip, lr}