From patchwork Tue Jan 6 16:37:10 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mathieu Poirier X-Patchwork-Id: 42792 Return-Path: X-Original-To: linaro@patches.linaro.org Delivered-To: linaro@patches.linaro.org Received: from mail-wg0-f70.google.com (mail-wg0-f70.google.com [74.125.82.70]) by ip-10-151-82-157.ec2.internal (Postfix) with ESMTPS id 244CD2062F for ; Tue, 6 Jan 2015 16:38:06 +0000 (UTC) Received: by mail-wg0-f70.google.com with SMTP id b13sf13264868wgh.1 for ; Tue, 06 Jan 2015 08:38:05 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:mime-version:delivered-to:from:to:cc:subject :date:message-id:in-reply-to:references:x-original-sender :x-original-authentication-results:precedence:mailing-list:list-id :list-post:list-help:list-archive:list-unsubscribe; bh=xFGtpRKez8jkycYfVhZaZe6GByXmlMVv64vI6oCDkMk=; b=b8olC7xS/OrDDJ8nYfIQkzvJE+pgwJ+HW88XnaQ0xs+cH6PaqLD7H1bKzRxFQGZ2Ur 1ZXEZhulumgkK/8DsC+uGhALQeiK2zXA9qBXxeph+aHrYu3EDyDTnmVgIbt32sZ1vxBH KrAxWHn+EjDD8qinIB92PMHj6Xq5U7YeH22/mbBrMlSwBo10OOf90lHbeuWyaQcEzy78 sfoTnK9bJIh4eTW2hIHn70sdXVmR/A9ZFl9UYtX3E5hm1sZD/HKvvZZ6LwbAhb3WiV2C 1lif6I4isvzFFHzxbKCMhI7Agzu/QLe9vEXU3nkwbFc2XosG7xfYE+KQIly1gZaDngDn 8MUQ== X-Gm-Message-State: ALoCoQmXR9oxSDh+wzGud9vlCIhwnf6NLX5D6rL3VDsNmRwIGPA2V2N6yM/QkPFf9VvFdXGVig9J X-Received: by 10.112.160.41 with SMTP id xh9mr358970lbb.12.1420562285265; Tue, 06 Jan 2015 08:38:05 -0800 (PST) MIME-Version: 1.0 X-BeenThere: patchwork-forward@linaro.org Received: by 10.152.198.235 with SMTP id jf11ls61268lac.74.gmail; Tue, 06 Jan 2015 08:38:05 -0800 (PST) X-Received: by 10.112.181.106 with SMTP id dv10mr96330006lbc.88.1420562285097; Tue, 06 Jan 2015 08:38:05 -0800 (PST) Received: from mail-la0-f46.google.com (mail-la0-f46.google.com. [209.85.215.46]) by mx.google.com with ESMTPS id bf5si66606584lab.62.2015.01.06.08.38.05 for (version=TLSv1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Tue, 06 Jan 2015 08:38:05 -0800 (PST) Received-SPF: pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.215.46 as permitted sender) client-ip=209.85.215.46; Received: by mail-la0-f46.google.com with SMTP id q1so20039633lam.5 for ; Tue, 06 Jan 2015 08:38:05 -0800 (PST) X-Received: by 10.112.104.4 with SMTP id ga4mr31290889lbb.24.1420562284993; Tue, 06 Jan 2015 08:38:04 -0800 (PST) X-Forwarded-To: patchwork-forward@linaro.org X-Forwarded-For: patch@linaro.org patchwork-forward@linaro.org Delivered-To: patches@linaro.org Received: by 10.112.9.200 with SMTP id c8csp1224919lbb; Tue, 6 Jan 2015 08:38:04 -0800 (PST) X-Received: by 10.68.78.68 with SMTP id z4mr81556522pbw.51.1420562274234; Tue, 06 Jan 2015 08:37:54 -0800 (PST) Received: from mail-pa0-f43.google.com (mail-pa0-f43.google.com. [209.85.220.43]) by mx.google.com with ESMTPS id wd6si27939993pab.204.2015.01.06.08.37.53 for (version=TLSv1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Tue, 06 Jan 2015 08:37:54 -0800 (PST) Received-SPF: pass (google.com: domain of mathieu.poirier@linaro.org designates 209.85.220.43 as permitted sender) client-ip=209.85.220.43; Received: by mail-pa0-f43.google.com with SMTP id kx10so31439107pab.30 for ; Tue, 06 Jan 2015 08:37:53 -0800 (PST) X-Received: by 10.66.163.196 with SMTP id yk4mr154450110pab.57.1420562273318; Tue, 06 Jan 2015 08:37:53 -0800 (PST) Received: from t430.cg.shawcable.net (S0106002369de4dac.cg.shawcable.net. [70.73.24.112]) by mx.google.com with ESMTPSA id iv1sm42245554pbc.87.2015.01.06.08.37.52 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 06 Jan 2015 08:37:52 -0800 (PST) From: mathieu.poirier@linaro.org To: liviu.dudau@arm.com, sudeep.holla@arm.com, lorenzo.pieralisi@arm.com Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, mathieu.poirier@linaro.org, patches@linaro.org Subject: [PATCH 6/9] coresight-etm3x: Fixing suspend/wake modes Date: Tue, 6 Jan 2015 09:37:10 -0700 Message-Id: <1420562233-2015-7-git-send-email-mathieu.poirier@linaro.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1420562233-2015-1-git-send-email-mathieu.poirier@linaro.org> References: <1420562233-2015-1-git-send-email-mathieu.poirier@linaro.org> X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: mathieu.poirier@linaro.org X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.215.46 as permitted sender) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Precedence: list Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org List-ID: X-Google-Group-Id: 836684582541 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , From: Mathieu Poirier This patch makes sure power is managed properly during power state transitions. Checks are introduced to make sure HW access functions aren't called uselessly to avoid wasting power and accessing blocks that may be powered down. Lastly the CPU_ONLINE state has been removed from the cpu callback as it wasn't useful anymore. Signed-off-by: Mathieu Poirier --- drivers/coresight/coresight-etm.h | 4 ++-- drivers/coresight/coresight-etm3x.c | 48 ++++++++++++++++++++----------------- 2 files changed, 28 insertions(+), 24 deletions(-) diff --git a/drivers/coresight/coresight-etm.h b/drivers/coresight/coresight-etm.h index 501c5fac8a45..a0e30ca2e32d 100644 --- a/drivers/coresight/coresight-etm.h +++ b/drivers/coresight/coresight-etm.h @@ -148,7 +148,7 @@ * @arch: ETM/PTM version number. * @use_cpu14: true if management registers need to be accessed via CP14. * @enable: is this ETM/PTM currently tracing. - * @sticky_enable: true if ETM base configuration has been done. + * @suspended: is the CPU associated to the ETM/PTM suspended? * @boot_enable:true if we should start tracing at boot time. * @os_unlock: true if access to management registers is allowed. * @nr_addr_cmp:Number of pairs of address comparators as found in ETMCCR. @@ -200,7 +200,7 @@ struct etm_drvdata { u8 arch; bool use_cp14; bool enable; - bool sticky_enable; + bool suspended; bool boot_enable; bool os_unlock; u8 nr_addr_cmp; diff --git a/drivers/coresight/coresight-etm3x.c b/drivers/coresight/coresight-etm3x.c index 7df9ffc51501..e09c3ef76d16 100644 --- a/drivers/coresight/coresight-etm3x.c +++ b/drivers/coresight/coresight-etm3x.c @@ -254,6 +254,12 @@ static void etm_enable_hw(void *info) u32 etmcr; struct etm_drvdata *drvdata = info; + if (clk_prepare_enable(drvdata->clk)) { + dev_dbg(drvdata->dev, "cpu: %d can't enable hw\n", + drvdata->cpu); + return; + } + pm_runtime_get_sync(drvdata->dev); CS_UNLOCK(drvdata->base); @@ -314,6 +320,8 @@ static void etm_enable_hw(void *info) etm_clr_prog(drvdata); CS_LOCK(drvdata->base); + drvdata->suspended = false; + dev_dbg(drvdata->dev, "cpu: %d enable smp call done\n", drvdata->cpu); } @@ -355,14 +363,12 @@ out: static int etm_enable(struct coresight_device *csdev) { struct etm_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent); - int ret; - - ret = clk_prepare_enable(drvdata->clk); - if (ret) - goto err_clk; + int ret = 0; spin_lock(&drvdata->spinlock); + if (drvdata->enable) + goto out; /* * Configure the ETM only if the CPU is online. If it isn't online * hw configuration will take place when 'CPU_STARTING' is received @@ -372,20 +378,17 @@ static int etm_enable(struct coresight_device *csdev) ret = smp_call_function_single(drvdata->cpu, etm_enable_hw, drvdata, 1); if (ret) - goto err; + goto out; } drvdata->enable = true; - drvdata->sticky_enable = true; - spin_unlock(&drvdata->spinlock); dev_info(drvdata->dev, "ETM tracing enabled\n"); return 0; -err: +out: spin_unlock(&drvdata->spinlock); clk_disable_unprepare(drvdata->clk); -err_clk: return ret; } @@ -397,6 +400,9 @@ static void etm_disable_hw(void *info) CS_UNLOCK(drvdata->base); etm_set_prog(drvdata); + if (!drvdata->enable) + return; + /* Program trace enable to low by using always false event */ etm_writel(drvdata, ETM_HARD_WIRE_RES_A | ETM_EVENT_NOT_A, ETMTEEVR); @@ -409,6 +415,9 @@ static void etm_disable_hw(void *info) etm_set_pwrdwn(drvdata); CS_LOCK(drvdata->base); pm_runtime_put_sync(drvdata->dev); + clk_disable_unprepare(drvdata->clk); + + drvdata->suspended = true; dev_dbg(drvdata->dev, "cpu: %d disable smp call done\n", drvdata->cpu); } @@ -426,18 +435,20 @@ static void etm_disable(struct coresight_device *csdev) get_online_cpus(); spin_lock(&drvdata->spinlock); + if (!drvdata->enable) + goto out; /* * Executing etm_disable_hw on the cpu whose ETM is being disabled * ensures that register writes occur when cpu is powered. */ - smp_call_function_single(drvdata->cpu, etm_disable_hw, drvdata, 1); + if (!drvdata->suspended) + smp_call_function_single(drvdata->cpu, + etm_disable_hw, drvdata, 1); drvdata->enable = false; - +out: spin_unlock(&drvdata->spinlock); put_online_cpus(); - clk_disable_unprepare(drvdata->clk); - dev_info(drvdata->dev, "ETM tracing disabled\n"); } @@ -1674,14 +1685,7 @@ static int etm_cpu_callback(struct notifier_block *nfb, unsigned long action, etm_enable_hw(etmdrvdata[cpu]); spin_unlock(&etmdrvdata[cpu]->spinlock); break; - - case CPU_ONLINE: - if (etmdrvdata[cpu]->boot_enable && - !etmdrvdata[cpu]->sticky_enable) - coresight_enable(etmdrvdata[cpu]->csdev); - break; - - case CPU_DYING: + case CPU_DEAD: spin_lock(&etmdrvdata[cpu]->spinlock); if (etmdrvdata[cpu]->enable) etm_disable_hw(etmdrvdata[cpu]);