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[209.132.180.67]) by mx.google.com with ESMTP id yz12si9480358pac.125.2014.11.07.08.27.53 for ; Fri, 07 Nov 2014 08:27:54 -0800 (PST) Received-SPF: none (google.com: linux-kernel-owner@vger.kernel.org does not designate permitted sender hosts) client-ip=209.132.180.67; Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752898AbaKGQ1l (ORCPT + 25 others); Fri, 7 Nov 2014 11:27:41 -0500 Received: from cam-admin0.cambridge.arm.com ([217.140.96.50]:48328 "EHLO cam-admin0.cambridge.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752736AbaKGQ1j (ORCPT ); Fri, 7 Nov 2014 11:27:39 -0500 Received: from leverpostej.cambridge.arm.com (leverpostej.cambridge.arm.com [10.1.205.151]) by cam-admin0.cambridge.arm.com (8.12.6/8.12.6) with ESMTP id sA7GPwx1014702; Fri, 7 Nov 2014 16:27:17 GMT From: Mark Rutland To: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org, will.deacon@arm.com, Mark Rutland Subject: [PATCH 11/11] arm: dts: vexpress: describe all PMUs in TC2 dts Date: Fri, 7 Nov 2014 16:25:36 +0000 Message-Id: <1415377536-12841-12-git-send-email-mark.rutland@arm.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1415377536-12841-1-git-send-email-mark.rutland@arm.com> References: <1415377536-12841-1-git-send-email-mark.rutland@arm.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: list List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: mark.rutland@arm.com X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.215.53 as permitted sender) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , The dts for the CoreTile Express A15x2 A7x3 (TC2) only describes the PMUs of the Cortex-A15 CPUs, and not the Cortex-A7 CPUs. Now that we have a mechanism for describing disparate PMUs and their interrupts in device tree, this patch makes use of these to describe the PMUs for all CPUs in the system. Signed-off-by: Mark Rutland --- arch/arm/boot/dts/vexpress-v2p-ca15_a7.dts | 36 +++++++++++++++++++++++++++++- 1 file changed, 35 insertions(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/vexpress-v2p-ca15_a7.dts b/arch/arm/boot/dts/vexpress-v2p-ca15_a7.dts index 322fd15..52416f9 100644 --- a/arch/arm/boot/dts/vexpress-v2p-ca15_a7.dts +++ b/arch/arm/boot/dts/vexpress-v2p-ca15_a7.dts @@ -90,6 +90,28 @@ min-residency-us = <2500>; }; }; + + cpu-map { + cluster0 { + core_0_0: core0 { + cpu = <&cpu0>; + }; + core_0_1: core1 { + cpu = <&cpu1>; + }; + }; + cluster1 { + core_1_0: core0 { + cpu = <&cpu2>; + }; + core_1_1: core1 { + cpu = <&cpu3>; + }; + core_1_2: core2 { + cpu = <&cpu4>; + }; + }; + }; }; memory@80000000 { @@ -187,10 +209,22 @@ <1 10 0xf08>; }; - pmu { + pmu_a15 { compatible = "arm,cortex-a15-pmu"; interrupts = <0 68 4>, <0 69 4>; + interrupts-affinity = <&core_0_0>, + <&core_0_1>; + }; + + pmu_a7 { + compatible = "arm,cortex-a7-pmu"; + interrupts = <0 128 4>, + <0 129 4>, + <0 130 4>; + interrupts-affinity = <&core_1_0>, + <&core_1_1>, + <&core_1_2>; }; oscclk6a: oscclk6a {