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[86.129.140.59]) by mx.google.com with ESMTPSA id rj6sm6663489igc.0.2014.11.05.09.00.29 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 05 Nov 2014 09:00:31 -0800 (PST) From: Lee Jones To: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Cc: lee.jones@linaro.org, kernel@stlinux.com, computersforpeace@gmail.com, pekon@pek-sem.com, linux-mtd@lists.infradead.org Subject: [PATCH v4 05/11] mtd: nand: Add new generic NAND Device Tree property 'nand-chip-select' Date: Wed, 5 Nov 2014 16:59:47 +0000 Message-Id: <1415206793-25670-6-git-send-email-lee.jones@linaro.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1415206793-25670-1-git-send-email-lee.jones@linaro.org> References: <1415206793-25670-1-git-send-email-lee.jones@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: list List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: lee.jones@linaro.org X-Original-Authentication-Results: mx.google.com; spf=temperror (google.com: error in processing during lookup of patch+caf_=patchwork-forward=linaro.org@linaro.org: DNS timeout) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , Signed-off-by: Lee Jones --- Documentation/devicetree/bindings/mtd/nand.txt | 3 +++ 1 file changed, 3 insertions(+) diff --git a/Documentation/devicetree/bindings/mtd/nand.txt b/Documentation/devicetree/bindings/mtd/nand.txt index b53f92e..1d542c51 100644 --- a/Documentation/devicetree/bindings/mtd/nand.txt +++ b/Documentation/devicetree/bindings/mtd/nand.txt @@ -12,6 +12,9 @@ - nand-ecc-step-size: integer representing the number of data bytes that are covered by a single ECC step. +- nand-chip-select: integer representing chip number associated with the + described Flash chip. + The ECC strength and ECC step size properties define the correction capability of a controller. Together, they say a controller can correct "{strength} bit errors per {size} bytes".