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[2001:1868:205::9]) by mx.google.com with ESMTPS id ff1si3571748pbb.132.2014.11.03.07.10.32 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 03 Nov 2014 07:10:33 -0800 (PST) Received-SPF: none (google.com: linux-arm-kernel-bounces+patch=linaro.org@lists.infradead.org does not designate permitted sender hosts) client-ip=2001:1868:205::9; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1XlJFg-0004lo-72; Mon, 03 Nov 2014 15:09:04 +0000 Received: from mail-pa0-f44.google.com ([209.85.220.44]) by bombadil.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1XlJFW-0004dE-CK for linux-arm-kernel@lists.infradead.org; Mon, 03 Nov 2014 15:08:55 +0000 Received: by mail-pa0-f44.google.com with SMTP id bj1so12349974pad.31 for ; Mon, 03 Nov 2014 07:08:33 -0800 (PST) X-Received: by 10.70.102.103 with SMTP id fn7mr1461509pdb.160.1415027313369; Mon, 03 Nov 2014 07:08:33 -0800 (PST) Received: from yogesh-Dell-System-Vostro-3360.Airtel4Grouter.cpe ([14.140.2.178]) by mx.google.com with ESMTPSA id mp5sm17413005pbc.33.2014.11.03.07.08.27 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 03 Nov 2014 07:08:32 -0800 (PST) From: Yogesh Tillu To: linux-arm-kernel@lists.infradead.org Subject: [RFC PATCH 2/5] Kernel module: to Enable userspace access to PMU counters for ArmV8 Date: Mon, 3 Nov 2014 20:34:02 +0530 Message-Id: <1415027045-6573-3-git-send-email-yogesh.tillu@linaro.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1415027045-6573-1-git-send-email-yogesh.tillu@linaro.org> References: <1415027045-6573-1-git-send-email-yogesh.tillu@linaro.org> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20141103_070854_598134_4E2CAC44 X-CRM114-Status: GOOD ( 12.62 ) X-Spam-Score: -0.7 (/) X-Spam-Report: SpamAssassin version 3.4.0 on bombadil.infradead.org summary: Content analysis details: (-0.7 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.7 RCVD_IN_DNSWL_LOW RBL: Sender listed at http://www.dnswl.org/, low trust [209.85.220.44 listed in list.dnswl.org] -0.0 SPF_PASS SPF: sender matches SPF record -0.0 RCVD_IN_MSPIKE_H2 RBL: Average reputation (+2) [209.85.220.44 listed in wl.mailspike.net] Cc: magnus.karlsson@avagotech.com, tillu.yogesh@gmail.com, Prasun.Kapoor@caviumnetworks.com, linux-perf-users@vger.kernel.org, Andrew.Pinski@caviumnetworks.com, mike.holmes@linaro.org, ola.liljedahl@linaro.org, Yogesh Tillu , linaro-networking@linaro.org, jean.pihet@linaro.org, arnd@linaro.org X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.18-1 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: , List-Help: , List-Subscribe: , MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patch=linaro.org@lists.infradead.org X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: yogesh.tillu@linaro.org X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.217.172 as permitted sender) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 This Patchset is for Kernel Module to Enable userspace access to PMU counters(ArmV8) Signed-off-by: Yogesh Tillu --- ARMv8_Module/Makefile | 8 ++++ ARMv8_Module/README | 1 + ARMv8_Module/enable_arm_pmu.c | 96 +++++++++++++++++++++++++++++++++++++++++ 3 files changed, 105 insertions(+) create mode 100644 ARMv8_Module/Makefile create mode 100644 ARMv8_Module/README create mode 100644 ARMv8_Module/enable_arm_pmu.c diff --git a/ARMv8_Module/Makefile b/ARMv8_Module/Makefile new file mode 100644 index 0000000..19a31ea --- /dev/null +++ b/ARMv8_Module/Makefile @@ -0,0 +1,8 @@ +obj-m := enable_arm_pmu.o +KDIR := /lib/modules/$(shell uname -r)/build +PWD := $(shell pwd) + +all: + $(MAKE) -C $(KDIR) SUBDIRS=$(PWD) modules +clean: + $(MAKE) -C $(KDIR) SUBDIRS=$(PWD) clean diff --git a/ARMv8_Module/README b/ARMv8_Module/README new file mode 100644 index 0000000..648456b --- /dev/null +++ b/ARMv8_Module/README @@ -0,0 +1 @@ +make ARCH=arm64 clean;make ARCH=arm64 CROSS_COMPILE=~/arm64-tc-14.06/bin/aarch64-linux-gnu- -C ~/work/lava_ci/juno/linux-linaro/workspace/builddir-3.16.0-linaro-juno/ SUBDIRS=`pwd` diff --git a/ARMv8_Module/enable_arm_pmu.c b/ARMv8_Module/enable_arm_pmu.c new file mode 100644 index 0000000..5c87b08 --- /dev/null +++ b/ARMv8_Module/enable_arm_pmu.c @@ -0,0 +1,96 @@ +/* + * Enable user-mode ARM performance counter access. + */ +#include +#include +#include +/** -- Configuration stuff ------------------------------------------------- */ + +#define DRVR_NAME "enable_arm_pmu" + +#if !defined(__aarch64__) + #error Module can only be compiled on ARM 64 machines. +#endif + +/** -- Initialization & boilerplate ---------------------------------------- */ + +#define PERF_DEF_OPTS (1 | 16) +#define PERF_OPT_RESET_CYCLES (2 | 4) +#define PERF_OPT_DIV64 (8) +#define ARMV8_PMCR_MASK 0x3f +#define ARMV8_PMCR_E (1 << 0) /* Enable all counters */ +#define ARMV8_PMCR_P (1 << 1) /* Reset all counters */ +#define ARMV8_PMCR_C (1 << 2) /* Cycle counter reset */ +#define ARMV8_PMCR_D (1 << 3) /* CCNT counts every 64th cpu cycle */ +#define ARMV8_PMCR_X (1 << 4) /* Export to ETM */ +#define ARMV8_PMCR_DP (1 << 5) /* Disable CCNT if non-invasive debug*/ +#define ARMV8_PMCR_N_SHIFT 11 /* Number of counters supported */ +#define ARMV8_PMCR_N_MASK 0x1f + +#define ARMV8_PMUSERENR_EN_EL0 (1 << 0) /* EL0 access enable */ +#define ARMV8_PMUSERENR_CR (1 << 2) /* Cycle counter read enable */ +#define ARMV8_PMUSERENR_ER (1 << 3) /* Event counter read enable */ + +static inline u32 armv8pmu_pmcr_read(void) +{ + u64 val=0; + asm volatile("mrs %0, pmcr_el0" : "=r" (val)); + return (u32)val; +} +static inline void armv8pmu_pmcr_write(u32 val) +{ + val &= ARMV8_PMCR_MASK; + isb(); + asm volatile("msr pmcr_el0, %0" : : "r" ((u64)val)); +} + +static void +enable_cpu_counters(void* data) +{ + u32 val=0; +/* Enable user-mode access to counters. */ + asm volatile("msr pmuserenr_el0, %0" : : "r"((u64)ARMV8_PMUSERENR_EN_EL0|ARMV8_PMUSERENR_ER|ARMV8_PMUSERENR_CR)); +/* Initialize & Reset PMNC: C and P bits. */ + armv8pmu_pmcr_write(ARMV8_PMCR_P | ARMV8_PMCR_C); +/*G4.4.11 +PMINTENSET, Performance Monitors Interrupt Enable Set register */ +/*cycle counter overflow interrupt request is disabled */ + asm volatile("msr pmintenset_el1, %0" : : "r" ((u64)(0 << 31))); +/*start*/ + armv8pmu_pmcr_write(armv8pmu_pmcr_read() | ARMV8_PMCR_E); +} + +static void +disable_cpu_counters(void* data) +{ + u32 val=0; + printk(KERN_INFO "\n [" DRVR_NAME "] disabling user-mode PMU access on CPU #%d", + smp_processor_id()); + + /* Program PMU and disable all counters */ + armv8pmu_pmcr_write(armv8pmu_pmcr_read() |~ARMV8_PMCR_E); + /* disable user-mode access to counters. */ + asm volatile("msr pmuserenr_el0, %0" : : "r"((u64)0)); + +} + +static int __init +init(void) +{ + on_each_cpu(enable_cpu_counters, NULL, 1); + printk(KERN_INFO "[" DRVR_NAME "] initialized"); + return 0; +} + +static void __exit +fini(void) +{ + on_each_cpu(disable_cpu_counters, NULL, 1); + printk(KERN_INFO "[" DRVR_NAME "] unloaded"); +} + +MODULE_AUTHOR("Yogesh Tillu "); +MODULE_DESCRIPTION("Enables user-mode access to ARMv8 PMU counters"); +MODULE_VERSION("0:0.1-dev"); +module_init(init); +module_exit(fini);