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[2001:1868:205::9]) by mx.google.com with ESMTPS id xq3si12750625pbb.253.2014.10.14.06.06.44 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 14 Oct 2014 06:06:45 -0700 (PDT) Received-SPF: none (google.com: linux-arm-kernel-bounces+patch=linaro.org@lists.infradead.org does not designate permitted sender hosts) client-ip=2001:1868:205::9; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1Xe1mk-0002Iv-GZ; Tue, 14 Oct 2014 13:05:06 +0000 Received: from mail-wg0-f45.google.com ([74.125.82.45]) by bombadil.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1Xe1me-00028Q-AG for linux-arm-kernel@lists.infradead.org; Tue, 14 Oct 2014 13:05:00 +0000 Received: by mail-wg0-f45.google.com with SMTP id m15so10734210wgh.28 for ; Tue, 14 Oct 2014 06:04:37 -0700 (PDT) X-Received: by 10.180.77.79 with SMTP id q15mr5434366wiw.8.1413291877799; Tue, 14 Oct 2014 06:04:37 -0700 (PDT) Received: from localhost.localdomain ([85.235.11.236]) by mx.google.com with ESMTPSA id hg14sm170558wib.24.2014.10.14.06.04.36 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 14 Oct 2014 06:04:36 -0700 (PDT) From: Linus Walleij To: linux-arm-kernel@lists.infradead.org Subject: [PATCH 2/8] ARM: realview: add PL061 GPIO to the PB1176 DTS Date: Tue, 14 Oct 2014 15:04:09 +0200 Message-Id: <1413291855-499-2-git-send-email-linus.walleij@linaro.org> X-Mailer: git-send-email 1.9.3 In-Reply-To: <1413291855-499-1-git-send-email-linus.walleij@linaro.org> References: <1413291855-499-1-git-send-email-linus.walleij@linaro.org> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20141014_060500_502705_22E92F28 X-CRM114-Status: GOOD ( 11.24 ) X-Spam-Score: -0.7 (/) X-Spam-Report: SpamAssassin version 3.4.0 on bombadil.infradead.org summary: Content analysis details: (-0.7 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.7 RCVD_IN_DNSWL_LOW RBL: Sender listed at http://www.dnswl.org/, low trust [74.125.82.45 listed in list.dnswl.org] -0.0 SPF_PASS SPF: sender matches SPF record -0.0 RCVD_IN_MSPIKE_H3 RBL: Good reputation (+3) [74.125.82.45 listed in wl.mailspike.net] -0.0 RCVD_IN_MSPIKE_WL Mailspike good senders Cc: Linus Walleij X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.18-1 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: , List-Help: , List-Subscribe: , MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patch=linaro.org@lists.infradead.org X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: linus.walleij@linaro.org X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.215.46 as permitted sender) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 This adds the PL061 GPIO instances found on the PB1176 devchip and the FPGA to the DTS file. Signed-off-by: Linus Walleij --- arch/arm/boot/dts/arm-realview-pb1176.dts | 39 +++++++++++++++++++++++++++++++ 1 file changed, 39 insertions(+) diff --git a/arch/arm/boot/dts/arm-realview-pb1176.dts b/arch/arm/boot/dts/arm-realview-pb1176.dts index f780adde2332..4721244a16d6 100644 --- a/arch/arm/boot/dts/arm-realview-pb1176.dts +++ b/arch/arm/boot/dts/arm-realview-pb1176.dts @@ -196,6 +196,19 @@ clock-names = "timer1", "timer2", "apb_pclk"; }; + pb1176_gpio0: gpio@1010a000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0x1010a000 0x1000>; + gpio-controller; + interrupt-parent = <&intc_dc1176>; + interrupts = <0 16 IRQ_TYPE_LEVEL_HIGH>; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&pclk>; + clock-names = "apb_pclk"; + }; + pb1176_serial0: serial@1010c000 { compatible = "arm,pl011", "arm,primecell"; reg = <0x1010c000 0x1000>; @@ -251,5 +264,31 @@ interrupt-parent = <&intc_dc1176>; interrupts = <0 31 IRQ_TYPE_LEVEL_HIGH>; }; + + fpga_gpio0: gpio@10014000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0x10014000 0x1000>; + gpio-controller; + interrupt-parent = <&intc_fpga1176>; + interrupts = <0 8 IRQ_TYPE_LEVEL_HIGH>; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&pclk>; + clock-names = "apb_pclk"; + }; + + fpga_gpio1: gpio@10015000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0x10015000 0x1000>; + gpio-controller; + interrupt-parent = <&intc_fpga1176>; + interrupts = <0 9 IRQ_TYPE_LEVEL_HIGH>; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&pclk>; + clock-names = "apb_pclk"; + }; }; };