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[2001:1868:205::9]) by mx.google.com with ESMTPS id dk4si12885734pbc.108.2014.10.14.06.06.38 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 14 Oct 2014 06:06:39 -0700 (PDT) Received-SPF: none (google.com: linux-arm-kernel-bounces+patch=linaro.org@lists.infradead.org does not designate permitted sender hosts) client-ip=2001:1868:205::9; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1Xe1mS-00029M-Ux; Tue, 14 Oct 2014 13:04:48 +0000 Received: from mail-wi0-f173.google.com ([209.85.212.173]) by bombadil.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1Xe1mQ-00027r-W4 for linux-arm-kernel@lists.infradead.org; Tue, 14 Oct 2014 13:04:47 +0000 Received: by mail-wi0-f173.google.com with SMTP id fb4so10078356wid.0 for ; Tue, 14 Oct 2014 06:04:23 -0700 (PDT) X-Received: by 10.180.188.41 with SMTP id fx9mr5172380wic.59.1413291863411; Tue, 14 Oct 2014 06:04:23 -0700 (PDT) Received: from localhost.localdomain ([85.235.11.236]) by mx.google.com with ESMTPSA id hg14sm170558wib.24.2014.10.14.06.04.21 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 14 Oct 2014 06:04:22 -0700 (PDT) From: Linus Walleij To: linux-arm-kernel@lists.infradead.org Subject: [PATCH 1/8] ARM: realview: move DT GIC to FPGA node Date: Tue, 14 Oct 2014 15:04:08 +0200 Message-Id: <1413291855-499-1-git-send-email-linus.walleij@linaro.org> X-Mailer: git-send-email 1.9.3 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20141014_060447_184068_6AD39407 X-CRM114-Status: GOOD ( 14.61 ) X-Spam-Score: -0.7 (/) X-Spam-Report: SpamAssassin version 3.4.0 on bombadil.infradead.org summary: Content analysis details: (-0.7 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.7 RCVD_IN_DNSWL_LOW RBL: Sender listed at http://www.dnswl.org/, low trust [209.85.212.173 listed in list.dnswl.org] -0.0 SPF_PASS SPF: sender matches SPF record -0.0 RCVD_IN_MSPIKE_H3 RBL: Good reputation (+3) [209.85.212.173 listed in wl.mailspike.net] -0.0 RCVD_IN_MSPIKE_WL Mailspike good senders Cc: Linus Walleij X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.18-1 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: , List-Help: , List-Subscribe: , MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patch=linaro.org@lists.infradead.org X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: linus.walleij@linaro.org X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.215.54 as permitted sender) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 This creates a node in the device tree to hold the FPGA devices as a "simple-bus" and moves the GIC found on the FPGA to this node, so it reflects the actual topology of the system. Signed-off-by: Linus Walleij --- arch/arm/boot/dts/arm-realview-pb1176.dts | 32 +++++++++++++++++++------------ 1 file changed, 20 insertions(+), 12 deletions(-) diff --git a/arch/arm/boot/dts/arm-realview-pb1176.dts b/arch/arm/boot/dts/arm-realview-pb1176.dts index 3135939cd13f..f780adde2332 100644 --- a/arch/arm/boot/dts/arm-realview-pb1176.dts +++ b/arch/arm/boot/dts/arm-realview-pb1176.dts @@ -153,18 +153,6 @@ <0x10120000 0x100>; }; - /* This GIC on the board is cascaded off the DevChip GIC */ - intc_pb1176: interrupt-controller@10040000 { - compatible = "arm,arm1176jzf-devchip-gic", "arm,arm11mp-gic"; - #interrupt-cells = <3>; - #address-cells = <1>; - interrupt-controller; - reg = <0x10041000 0x1000>, - <0x10040000 0x100>; - interrupt-parent = <&intc_dc1176>; - interrupts = <0 31 IRQ_TYPE_LEVEL_HIGH>; - }; - L2: l2-cache { compatible = "arm,l220-cache"; reg = <0x10110000 0x1000>; @@ -244,4 +232,24 @@ clock-names = "uartclk", "apb_pclk"; }; }; + + /* These peripherals are inside the FPGA rather than the DevChip */ + fpga { + #address-cells = <1>; + #size-cells = <1>; + compatible = "simple-bus"; + ranges; + + /* This GIC on the board is cascaded off the DevChip GIC */ + intc_fpga1176: interrupt-controller@10040000 { + compatible = "arm,arm1176jzf-devchip-gic", "arm,arm11mp-gic"; + #interrupt-cells = <3>; + #address-cells = <1>; + interrupt-controller; + reg = <0x10041000 0x1000>, + <0x10040000 0x100>; + interrupt-parent = <&intc_dc1176>; + interrupts = <0 31 IRQ_TYPE_LEVEL_HIGH>; + }; + }; };