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[209.132.180.67]) by mx.google.com with ESMTP id un7si15934730pac.87.2014.09.17.19.15.19 for ; Wed, 17 Sep 2014 19:15:20 -0700 (PDT) Received-SPF: none (google.com: linux-kernel-owner@vger.kernel.org does not designate permitted sender hosts) client-ip=209.132.180.67; Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1757478AbaIRCPO (ORCPT + 27 others); Wed, 17 Sep 2014 22:15:14 -0400 Received: from mail-bn1bon0145.outbound.protection.outlook.com ([157.56.111.145]:53920 "EHLO na01-bn1-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1756686AbaIRCPK (ORCPT ); Wed, 17 Sep 2014 22:15:10 -0400 Received: from BY2PR02CA002.namprd02.prod.outlook.com (10.255.247.22) by CO1PR02MB208.namprd02.prod.outlook.com (10.242.165.150) with Microsoft SMTP Server (TLS) id 15.0.1034.13; Thu, 18 Sep 2014 02:15:07 +0000 Received: from BN1BFFO11FD012.protection.gbl (2a01:111:f400:7c10::1:199) by BY2PR02CA002.outlook.office365.com (2a01:111:e400:2c16::22) with Microsoft SMTP Server (TLS) id 15.0.1034.13 via Frontend Transport; Thu, 18 Sep 2014 02:15:06 +0000 Received: from atltwp01.amd.com (165.204.84.221) by BN1BFFO11FD012.mail.protection.outlook.com (10.58.144.75) with Microsoft SMTP Server id 15.0.1029.15 via Frontend Transport; Thu, 18 Sep 2014 02:15:06 +0000 X-WSS-ID: 0NC2RL3-07-G1T-02 X-M-MSG: Received: from satlvexedge02.amd.com (satlvexedge02.amd.com [10.177.96.29]) (using TLSv1 with cipher AES128-SHA (128/128 bits)) (No client certificate requested) by atltwp01.amd.com (Axway MailGate 5.3.1) with ESMTPS id 23DB0CAE65D; Wed, 17 Sep 2014 21:15:03 -0500 (CDT) Received: from SATLEXDAG01.amd.com (10.181.40.3) by SATLVEXEDGE02.amd.com (10.177.96.29) with Microsoft SMTP Server (TLS) id 14.3.195.1; Wed, 17 Sep 2014 21:15:15 -0500 Received: from ssuthiku-fedora-lt.amd.com (10.180.168.240) by SATLEXDAG01.amd.com (10.181.40.3) with Microsoft SMTP Server id 14.3.195.1; Wed, 17 Sep 2014 22:15:02 -0400 From: To: , , CC: , , , , , , , , , , , "Suravee Suthikulpanit" , Mark Rutland , Marc Zyngier Subject: [PATCH 1/2 V7] irqchip: gic: Add support for multiple MSI for ARM64 Date: Wed, 17 Sep 2014 19:14:45 -0700 Message-ID: <1411006486-17513-2-git-send-email-suravee.suthikulpanit@amd.com> X-Mailer: git-send-email 1.9.3 In-Reply-To: <1411006486-17513-1-git-send-email-suravee.suthikulpanit@amd.com> References: <1411006486-17513-1-git-send-email-suravee.suthikulpanit@amd.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-Forefront-Antispam-Report: CIP:165.204.84.221; CTRY:US; IPV:NLI; EFV:NLI; SFV:NSPM; SFS:(10019020)(6009001)(428002)(199003)(189002)(19580405001)(83322001)(21056001)(50986999)(83072002)(229853001)(19580395003)(107046002)(68736004)(89996001)(33646002)(76176999)(64706001)(95666004)(47776003)(20776003)(88136002)(104166001)(87936001)(92726001)(53416004)(2201001)(87286001)(92566001)(86152002)(44976005)(85306004)(99396002)(101416001)(77156001)(85852003)(62966002)(36756003)(84676001)(93916002)(106466001)(97736003)(4396001)(80022003)(74502003)(79102003)(77982003)(81542003)(81342003)(86362001)(46102003)(74662003)(77096002)(105586002)(50466002)(90102001)(31966008)(48376002)(50226001)(2004002); DIR:OUT; SFP:1102; SCL:1; SRVR:CO1PR02MB208; H:atltwp01.amd.com; FPR:; MLV:sfv; PTR:InfoDomainNonexistent; A:1; MX:1; LANG:en; X-Microsoft-Antispam: UriScan:; X-Microsoft-Antispam: BCL:0;PCL:0;RULEID:;SRVR:CO1PR02MB208; X-Forefront-PRVS: 033857D0BD Received-SPF: None (protection.outlook.com: amd.com does not designate permitted sender hosts) X-OriginatorOrg: amd4.onmicrosoft.com Sender: linux-kernel-owner@vger.kernel.org Precedence: list List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: suravee.suthikulpanit@amd.com X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.217.181 as permitted sender) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , From: Suravee Suthikulpanit This patch implelments the ARM64 version of arch_setup_msi_irqs(), which does not return 1 for when PCI_CAP_ID_MSI and nvec > 1. Cc: Mark Rutland Cc: Marc Zyngier Cc: Jason Cooper Cc: Catalin Marinas Cc: Will Deacon Signed-off-by: Suravee Suthikulpanit Acked-by: Marc Zyngier --- arch/arm64/kernel/Makefile | 1 + arch/arm64/kernel/msi.c | 41 +++++++++++++++++++++++++++++++++++++++++ 2 files changed, 42 insertions(+) create mode 100644 arch/arm64/kernel/msi.c diff --git a/arch/arm64/kernel/Makefile b/arch/arm64/kernel/Makefile index df7ef87..a921c42 100644 --- a/arch/arm64/kernel/Makefile +++ b/arch/arm64/kernel/Makefile @@ -29,6 +29,7 @@ arm64-obj-$(CONFIG_ARM64_CPU_SUSPEND) += sleep.o suspend.o arm64-obj-$(CONFIG_JUMP_LABEL) += jump_label.o arm64-obj-$(CONFIG_KGDB) += kgdb.o arm64-obj-$(CONFIG_EFI) += efi.o efi-stub.o efi-entry.o +arm64-obj-$(CONFIG_PCI_MSI) += msi.o obj-y += $(arm64-obj-y) vdso/ obj-m += $(arm64-obj-m) diff --git a/arch/arm64/kernel/msi.c b/arch/arm64/kernel/msi.c new file mode 100644 index 0000000..a295862 --- /dev/null +++ b/arch/arm64/kernel/msi.c @@ -0,0 +1,41 @@ +/* + * ARM64 architectural MSI implemention + * + * Support for Message Signalelled Interrupts for systems that + * implement ARM Generic Interrupt Controller: GICv2m. + * + * Copyright (C) 2014 Advanced Micro Devices, Inc. + * Authors: Suravee Suthikulpanit + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include +#include +#include + +/* + * ARM64 function for seting up MSI irqs. + * Based on driver/pci/msi.c: arch_setup_msi_irqs(). + * + * Note: + * Current implementation assumes that all interrupt controller used in + * ARM64 architecture _MUST_ supports multi-MSI. + */ +int arm64_setup_msi_irqs(struct pci_dev *dev, int nvec, int type) +{ + struct msi_desc *entry; + int ret; + + list_for_each_entry(entry, &dev->msi_list, list) { + ret = arch_setup_msi_irq(dev, entry); + if (ret < 0) + return ret; + if (ret > 0) + return -ENOSPC; + } + + return 0; +}