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[2001:1868:205::9]) by mx.google.com with ESMTPS id pm2si6201911pdb.74.2014.09.12.00.39.45 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 12 Sep 2014 00:39:45 -0700 (PDT) Received-SPF: none (google.com: linux-arm-kernel-bounces+patch=linaro.org@lists.infradead.org does not designate permitted sender hosts) client-ip=2001:1868:205::9; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1XSLR4-0001KC-Nm; Fri, 12 Sep 2014 07:38:26 +0000 Received: from mail-wi0-f180.google.com ([209.85.212.180]) by bombadil.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1XSLQx-0000xg-Na for linux-arm-kernel@lists.infradead.org; Fri, 12 Sep 2014 07:38:20 +0000 Received: by mail-wi0-f180.google.com with SMTP id ex7so85056wid.7 for ; Fri, 12 Sep 2014 00:37:57 -0700 (PDT) X-Received: by 10.194.205.196 with SMTP id li4mr8443474wjc.46.1410507477248; Fri, 12 Sep 2014 00:37:57 -0700 (PDT) Received: from localhost.localdomain ([85.235.11.236]) by mx.google.com with ESMTPSA id wr8sm3610466wjb.20.2014.09.12.00.37.55 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 12 Sep 2014 00:37:56 -0700 (PDT) From: Linus Walleij To: linux-arm-kernel@lists.infradead.org, dmaengine@vger.kernel.org, Vinod Koul , Roland Stigge , Arnd Bergmann Subject: [PATCH 4/4] ARM: nomadik: add DMA support Date: Fri, 12 Sep 2014 09:37:52 +0200 Message-Id: <1410507472-32530-1-git-send-email-linus.walleij@linaro.org> X-Mailer: git-send-email 1.9.3 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20140912_003820_081445_630C41CC X-CRM114-Status: GOOD ( 12.11 ) X-Spam-Score: -0.7 (/) X-Spam-Report: SpamAssassin version 3.4.0 on bombadil.infradead.org summary: Content analysis details: (-0.7 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.7 RCVD_IN_DNSWL_LOW RBL: Sender listed at http://www.dnswl.org/, low trust [209.85.212.180 listed in list.dnswl.org] -0.0 SPF_PASS SPF: sender matches SPF record -0.0 RCVD_IN_MSPIKE_H3 RBL: Good reputation (+3) [209.85.212.180 listed in wl.mailspike.net] -0.0 RCVD_IN_MSPIKE_WL Mailspike good senders Cc: Dan Williams , Russell King , Linus Walleij X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.18-1 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: , List-Help: , List-Subscribe: , MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patch=linaro.org@lists.infradead.org X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: linus.walleij@linaro.org X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.217.181 as permitted sender) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 This adds DMA controller entries for the two PL08x blocks on the Nomadik, assigns the fixed signal names, and defines channels for UART and MMC/SD. Tested on the S8815 USB dongle. Signed-off-by: Linus Walleij --- arch/arm/boot/dts/ste-nomadik-stn8815.dtsi | 296 +++++++++++++++++++++++++++++ 1 file changed, 296 insertions(+) diff --git a/arch/arm/boot/dts/ste-nomadik-stn8815.dtsi b/arch/arm/boot/dts/ste-nomadik-stn8815.dtsi index dbcf521b017f..8ffe68d9f670 100644 --- a/arch/arm/boot/dts/ste-nomadik-stn8815.dtsi +++ b/arch/arm/boot/dts/ste-nomadik-stn8815.dtsi @@ -794,6 +794,10 @@ clock-names = "uartclk", "apb_pclk"; pinctrl-names = "default"; pinctrl-0 = <&uart0_default_mux>; + dmas = <&dmac0 14>, + <&dmac0 15>; + dma-names = "rx", "tx"; + }; uart1: uart@101fb000 { @@ -805,6 +809,9 @@ clock-names = "uartclk", "apb_pclk"; pinctrl-names = "default"; pinctrl-0 = <&uart1_default_mux>; + dmas = <&dmac1 22>, + <&dmac1 23>; + dma-names = "rx", "tx"; }; uart2: uart@101f2000 { @@ -848,6 +855,295 @@ pinctrl-names = "default"; pinctrl-0 = <&mmcsd_default_mux>, <&mmcsd_default_mode>; vmmc-supply = <&vmmc_regulator>; + dmas = <&dmac1 21>; + dma-names = "rx"; + }; + + dmac0: dma-controller@10130000 { + compatible = "arm,pl080", "arm,primecell"; + reg = <0x10130000 0x1000>; + interrupt-parent = <&vica>; + interrupts = <15>; + clocks = <&hclkdma0>; + clock-names = "apb_pclk"; + lli-bus-interface-ahb1; + lli-bus-interface-ahb2; + mem-bus-interface-ahb2; + memcpy-burst-size = <256>; + memcpy-bus-width = <32>; + #dma-cells = <1>; + /* Assignments for the 32 channels */ + saa0@dmac0 { + signal = "saa0"; + bus-interface-ahb1; + }; + saa1@dmac0 { + signal = "saa1"; + bus-interface-ahb1; + }; + saa2@dmac0 { + signal = "saa2"; + bus-interface-ahb1; + }; + saa3@dmac0 { + signal = "saa3"; + bus-interface-ahb1; + }; + saa4@dmac0 { + signal = "saa4"; + bus-interface-ahb1; + }; + saa5@dmac0 { + signal = "saa5"; + bus-interface-ahb1; + }; + saa6@dmac0 { + signal = "saa6"; + bus-interface-ahb1; + }; + saa7@dmac0 { + signal = "saa7"; + bus-interface-ahb1; + }; + unused@dmac0 { + signal = "unused"; + bus-interface-ahb1; + }; + fir@dmac0 { + signal = "firdatxrx"; + bus-interface-ahb1; + }; + msp0rx@dmac0 { + signal = "msp0rx"; + bus-interface-ahb1; + }; + msp0tx@dmac0 { + signal = "msp0tx"; + bus-interface-ahb1; + }; + ssprx@dmac0 { + signal = "ssprx"; + bus-interface-ahb1; + }; + ssptx@dmac0 { + signal = "ssptx"; + bus-interface-ahb1; + }; + uart0rx@dmac0 { + signal = "uart0rx"; + bus-interface-ahb1; + }; + uart0tx@dmac0 { + signal = "uart0tx"; + bus-interface-ahb1; + }; + hsirxch0@dmac0 { + signal = "hsirxch0"; + bus-interface-ahb1; + }; + hsirxch1@dmac0 { + signal = "hsirxch1"; + bus-interface-ahb1; + }; + hsirxch2@dmac0 { + signal = "hsirxch2"; + bus-interface-ahb1; + }; + hsirxch3@dmac0 { + signal = "hsirxch3"; + bus-interface-ahb1; + }; + hsirxch4@dmac0 { + signal = "hsirxch4"; + bus-interface-ahb1; + }; + hsirxch5@dmac0 { + signal = "hsirxch5"; + bus-interface-ahb1; + }; + hsirxch6@dmac0 { + signal = "hsirxch6"; + bus-interface-ahb1; + }; + hsirxch7@dmac0 { + signal = "hsirxch7"; + bus-interface-ahb1; + }; + hsitxch0@dmac0 { + signal = "hsitxch0"; + bus-interface-ahb1; + }; + hsitxch1@dmac0 { + signal = "hsitxch1"; + bus-interface-ahb1; + }; + hsitxch2@dmac0 { + signal = "hsitxch2"; + bus-interface-ahb1; + }; + hsitxch3@dmac0 { + signal = "hsitxch3"; + bus-interface-ahb1; + }; + hsitxch4@dmac0 { + signal = "hsitxch4"; + bus-interface-ahb1; + }; + hsitxch5@dmac0 { + signal = "hsitxch5"; + bus-interface-ahb1; + }; + hsitxch6@dmac0 { + signal = "hsitxch6"; + bus-interface-ahb1; + }; + hsitxch7@dmac0 { + signal = "hsitxch7"; + bus-interface-ahb1; + }; + }; + dmac1: dma-controller@10150000 { + compatible = "arm,pl080", "arm,primecell"; + reg = <0x10150000 0x1000>; + interrupt-parent = <&vica>; + interrupts = <13>; + clocks = <&hclkdma1>; + clock-names = "apb_pclk"; + lli-bus-interface-ahb1; + lli-bus-interface-ahb2; + mem-bus-interface-ahb2; + memcpy-burst-size = <256>; + memcpy-bus-width = <32>; + #dma-cells = <1>; + /* Assignments for the 32 channels */ + saa0@dmac1 { + signal = "saa0"; + bus-interface-ahb1; + }; + saa1@dmac1 { + signal = "saa1"; + bus-interface-ahb1; + }; + saa2@dmac1 { + signal = "saa2"; + bus-interface-ahb1; + }; + saa3@dmac1 { + signal = "saa3"; + bus-interface-ahb1; + }; + saa4@dmac1 { + signal = "saa4"; + bus-interface-ahb1; + }; + saa5@dmac1 { + signal = "saa5"; + bus-interface-ahb1; + }; + saa6@dmac1 { + signal = "saa6"; + bus-interface-ahb1; + }; + saa7@dmac1 { + signal = "saa7"; + bus-interface-ahb1; + }; + unused@dmac1 { + signal = "unused"; + bus-interface-ahb1; + }; + fir@dmac1 { + signal = "firdatxrx"; + bus-interface-ahb1; + }; + msp0rx@dmac1 { + signal = "msp0rx"; + bus-interface-ahb1; + }; + msp0tx@dmac1 { + signal = "msp0tx"; + bus-interface-ahb1; + }; + ssprx@dmac1 { + signal = "ssprx"; + bus-interface-ahb1; + }; + ssptx@dmac1 { + signal = "ssptx"; + bus-interface-ahb1; + }; + uart0rx@dmac1 { + signal = "uart0rx"; + bus-interface-ahb1; + }; + uart0tx@dmac1 { + signal = "uart0tx"; + bus-interface-ahb1; + }; + tdesin@dmac1 { + signal = "tdesin"; + bus-interface-ahb1; + }; + tdesout@dmac1 { + signal = "tdesout"; + bus-interface-ahb1; + }; + i2c1rxtx@dmac1 { + signal = "i2c1rxtx"; + bus-interface-ahb1; + }; + i2c0rxtx@dmac1 { + signal = "i2c0rxtx"; + bus-interface-ahb1; + }; + sha1@dmac1 { + signal = "sha1"; + bus-interface-ahb1; + }; + sdirxtx@dmac1 { + signal = "sdirxtx"; + bus-interface-ahb1; + }; + uart1rxdmac1 { + signal = "uart1rx"; + bus-interface-ahb1; + }; + uart1tx@dmac1 { + signal = "uart1tx"; + bus-interface-ahb1; + }; + usbotg0@dmac1 { + signal = "usbotg0"; + bus-interface-ahb1; + }; + usbotg1@dmac1 { + signal = "usbotg1"; + bus-interface-ahb1; + }; + usbotg2@dmac1 { + signal = "usbotg2"; + bus-interface-ahb1; + }; + usbotg3@dmac1 { + signal = "usbotg3"; + bus-interface-ahb1; + }; + usbotg4@dmac1 { + signal = "usbotg4"; + bus-interface-ahb1; + }; + usbotg5@dmac1 { + signal = "usbotg5"; + bus-interface-ahb1; + }; + usbotg6@dmac1 { + signal = "usbotg6"; + bus-interface-ahb1; + }; + usbotg7@dmac1 { + signal = "usbotg7"; + bus-interface-ahb1; + }; }; }; };