From patchwork Fri Sep 12 07:37:22 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Linus Walleij X-Patchwork-Id: 37285 Return-Path: X-Original-To: linaro@patches.linaro.org Delivered-To: linaro@patches.linaro.org Received: from mail-we0-f200.google.com (mail-we0-f200.google.com [74.125.82.200]) by ip-10-151-82-157.ec2.internal (Postfix) with ESMTPS id C842D203EE for ; Fri, 12 Sep 2014 07:37:34 +0000 (UTC) Received: by mail-we0-f200.google.com with SMTP id u57sf201113wes.11 for ; Fri, 12 Sep 2014 00:37:33 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:mime-version:delivered-to:from:to:cc:subject :date:message-id:sender:precedence:list-id:x-original-sender :x-original-authentication-results:mailing-list:list-post:list-help :list-archive:list-unsubscribe; bh=pjRAZF2jO21F2Z7doHKKidC8jhY9zzilfXtk+5hFwNM=; b=CtQNl6T+PUDhcR7xgpCsJdjDgoFEsUIcJGkcd/FF89tOi5pB8hw7jO/ujd4r0Yp8of M38EpG2UiGyLfZ0qrEl0iW83tjA/29u7uCwM2lnf2D4kaYdei79s+MC4eEdSk6vyj95F yNr87qe/H1ClWiXVtD3IsHurxtw9biIdOB7XtyW/flV3e9QwJ4K5yeJcMhO080i6Ms7P SE/uIbjwgyyt0NpUrc+1HQfEQe7NNuFT3uklMtGcZN/Gh20gr1VF9GJVdmjZ0wBHNE07 C+seAI2qpYyj6Fdw0o14U5S8iCcZM/8I0iQsHB3GFy2NzjEUhyTPOm4UXfp/KURLk7hl 4OaQ== X-Gm-Message-State: ALoCoQkkbFthpTVUDivpMANNd+WIejs7W/YLtFJLFaNz1PIr1YwMd24S76njYAsprMjryCVinD1/ X-Received: by 10.180.206.66 with SMTP id lm2mr45486wic.1.1410507453946; Fri, 12 Sep 2014 00:37:33 -0700 (PDT) MIME-Version: 1.0 X-BeenThere: patchwork-forward@linaro.org Received: by 10.152.121.10 with SMTP id lg10ls139327lab.74.gmail; Fri, 12 Sep 2014 00:37:33 -0700 (PDT) X-Received: by 10.152.21.98 with SMTP id u2mr6888766lae.80.1410507453785; Fri, 12 Sep 2014 00:37:33 -0700 (PDT) Received: from mail-la0-f41.google.com (mail-la0-f41.google.com [209.85.215.41]) by mx.google.com with ESMTPS id h10si5007375lam.113.2014.09.12.00.37.33 for (version=TLSv1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Fri, 12 Sep 2014 00:37:33 -0700 (PDT) Received-SPF: pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.215.41 as permitted sender) client-ip=209.85.215.41; Received: by mail-la0-f41.google.com with SMTP id s18so402990lam.0 for ; Fri, 12 Sep 2014 00:37:33 -0700 (PDT) X-Received: by 10.152.5.168 with SMTP id t8mr6584443lat.67.1410507453473; Fri, 12 Sep 2014 00:37:33 -0700 (PDT) X-Forwarded-To: patchwork-forward@linaro.org X-Forwarded-For: patch@linaro.org patchwork-forward@linaro.org Delivered-To: patch@linaro.org Received: by 10.112.141.42 with SMTP id rl10csp686483lbb; Fri, 12 Sep 2014 00:37:32 -0700 (PDT) X-Received: by 10.70.87.134 with SMTP id ay6mr9874435pdb.68.1410507451906; Fri, 12 Sep 2014 00:37:31 -0700 (PDT) Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id ti10si5977642pab.206.2014.09.12.00.37.31 for ; Fri, 12 Sep 2014 00:37:31 -0700 (PDT) Received-SPF: none (google.com: devicetree-owner@vger.kernel.org does not designate permitted sender hosts) client-ip=209.132.180.67; Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752817AbaILHha (ORCPT + 5 others); Fri, 12 Sep 2014 03:37:30 -0400 Received: from mail-wg0-f49.google.com ([74.125.82.49]:54227 "EHLO mail-wg0-f49.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752643AbaILHh3 (ORCPT ); Fri, 12 Sep 2014 03:37:29 -0400 Received: by mail-wg0-f49.google.com with SMTP id m15so295945wgh.8 for ; Fri, 12 Sep 2014 00:37:28 -0700 (PDT) X-Received: by 10.180.90.207 with SMTP id by15mr15576wib.76.1410507448578; Fri, 12 Sep 2014 00:37:28 -0700 (PDT) Received: from localhost.localdomain ([85.235.11.236]) by mx.google.com with ESMTPSA id m9sm3588469wjz.35.2014.09.12.00.37.26 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 12 Sep 2014 00:37:27 -0700 (PDT) From: Linus Walleij To: linux-arm-kernel@lists.infradead.org, dmaengine@vger.kernel.org, Vinod Koul , Roland Stigge , Arnd Bergmann , devicetree@vger.kernel.org Cc: Russell King , Dan Williams , Linus Walleij Subject: [PATCH 2/4] dmaengine: device tree bindings for PL08x Date: Fri, 12 Sep 2014 09:37:22 +0200 Message-Id: <1410507442-32451-1-git-send-email-linus.walleij@linaro.org> X-Mailer: git-send-email 1.9.3 Sender: devicetree-owner@vger.kernel.org Precedence: list List-ID: X-Mailing-List: devicetree@vger.kernel.org X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: linus.walleij@linaro.org X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.215.41 as permitted sender) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , This introduces device tree bindings for the PL08x DMA controllers when used with fixed signal assignment per channel, i.e. if each channel on the PL08x is assigned precisely one burst/single signal set. In many incarnations that exist in the wild, a mux had been put in front of the signals so that the system has to select a subset of signals to handle from a larger set. This is not described in the current binding: instead this is assumed to be handled with a more elaborate binding especially for muxed signal cases. I imagine things like adding the property dma-mux = <&phandle>; for the DMA controller in such cases, and not specifying any signals for the channels, and provide a separate binding for the mux to enlist its signals. Signed-off-by: Linus Walleij --- .../devicetree/bindings/dma/arm-pl08x.txt | 182 +++++++++++++++++++++ 1 file changed, 182 insertions(+) create mode 100644 Documentation/devicetree/bindings/dma/arm-pl08x.txt diff --git a/Documentation/devicetree/bindings/dma/arm-pl08x.txt b/Documentation/devicetree/bindings/dma/arm-pl08x.txt new file mode 100644 index 000000000000..5e0aca09b56b --- /dev/null +++ b/Documentation/devicetree/bindings/dma/arm-pl08x.txt @@ -0,0 +1,182 @@ +* ARM PrimeCells PL080 and PL081 and derivatives DMA controller + +Required properties: +- compatible: "arm,pl080", "arm,pl081", "arm,primecell" +- reg: Address range of the PL08x registers +- interrupt: The PL08x interrupt number +- clocks: The clock running the IP core clock +- clock-names: A list with one element with the name of the core clock +- lli-bus-interface-ahb1: if AHB master 1 is eligible for fetching LLIs +- lli-bus-interface-ahb2: if AHB master 2 is eligible for fetching LLIs +- mem-bus-interface-ahb1: if AHB master 1 is eligible for fetching memory contents +- mem-bus-interface-ahb2: if AHB master 2 is eligible for fetching memory contents +- #dma-cells: must be <3> + +Optional properties: +- memcpy-burst-size: the size of the bursts for memcpy: 1, 4, 8, 16, 32 + 64, 128 or 256 bytes are legal values +- memcpy-bus-width: the bus width used for memcpy: 8, 16 or 32 are legal + values + +Optional sub-nodes: +The slave transfer channels are assigned in consecutive order and +identified by one child node per channel, assuming a fixed-signal +per channel assignment and each with the following properties: + +Required properties: +- signal: the name of the on-chip signal line handled by this channel +- bus-interface-ahb1 or bus-interface-ahb2: tells the driver which + bus interface(s) that is eligible for this specific channel. At least + one of the interfaces must be specified, it is perfectly legal to + specify both if the hardware supports using either interface. + +Clients +Required properties: +- dmas: Comma separated list of dma channel requests +- dma-names: Names of the aforementioned requested channels + +Example: + +dmac0: dma-controller@10130000 { + compatible = "arm,pl080", "arm,primecell"; + reg = <0x10130000 0x1000>; + interrupt-parent = <&vica>; + interrupts = <15>; + clocks = <&hclkdma0>; + clock-names = "apb_pclk"; + lli-bus-interface-ahb1; + lli-bus-interface-ahb2; + mem-bus-interface-ahb2; + memcpy-burst-size = <256>; + memcpy-bus-width = <32>; + #dma-cells = <1>; + /* Assignments for the 32 channels */ + saa0@dmac0 { + signal = "saa0"; + bus-interface-ahb1; + }; + saa1@dmac0 { + signal = "saa1"; + bus-interface-ahb1; + }; + saa2@dmac0 { + signal = "saa2"; + bus-interface-ahb1; + }; + saa3@dmac0 { + signal = "saa3"; + bus-interface-ahb1; + }; + saa4@dmac0 { + signal = "saa4"; + bus-interface-ahb1; + }; + saa5@dmac0 { + signal = "saa5"; + bus-interface-ahb1; + }; + saa6@dmac0 { + signal = "saa6"; + bus-interface-ahb1; + }; + saa7@dmac0 { + signal = "saa7"; + bus-interface-ahb1; + }; + unused@dmac0 { + signal = "unused"; + bus-interface-ahb1; + }; + fir@dmac0 { + signal = "firdatxrx"; + bus-interface-ahb1; + }; + msp0rx@dmac0 { + signal = "msp0rx"; + bus-interface-ahb1; + }; + msp0tx@dmac0 { + signal = "msp0tx"; + bus-interface-ahb1; + }; + ssprx@dmac0 { + signal = "ssprx"; + bus-interface-ahb1; + }; + ssptx@dmac0 { + signal = "ssptx"; + bus-interface-ahb1; + }; + uart0rx@dmac0 { + signal = "uart0rx"; + bus-interface-ahb1; + }; + uart0tx@dmac0 { + signal = "uart0tx"; + bus-interface-ahb1; + }; + hsirxch0@dmac0 { + signal = "hsirxch0"; + bus-interface-ahb1; + }; + hsirxch1@dmac0 { + signal = "hsirxch1"; + bus-interface-ahb1; + }; + hsirxch2@dmac0 { + signal = "hsirxch2"; + bus-interface-ahb1; + }; + hsirxch3@dmac0 { + signal = "hsirxch3"; + bus-interface-ahb1; + }; + hsirxch4@dmac0 { + signal = "hsirxch4"; + bus-interface-ahb1; + }; + hsirxch5@dmac0 { + signal = "hsirxch5"; + bus-interface-ahb1; + }; + hsirxch6@dmac0 { + signal = "hsirxch6"; + bus-interface-ahb1; + }; + hsirxch7@dmac0 { + signal = "hsirxch7"; + bus-interface-ahb1; + }; + hsitxch0@dmac0 { + signal = "hsitxch0"; + bus-interface-ahb1; + }; + hsitxch1@dmac0 { + signal = "hsitxch1"; + bus-interface-ahb1; + }; + hsitxch2@dmac0 { + signal = "hsitxch2"; + bus-interface-ahb1; + }; + hsitxch3@dmac0 { + signal = "hsitxch3"; + bus-interface-ahb1; + }; + hsitxch4@dmac0 { + signal = "hsitxch4"; + bus-interface-ahb1; + }; + hsitxch5@dmac0 { + signal = "hsitxch5"; + bus-interface-ahb1; + }; + hsitxch6@dmac0 { + signal = "hsitxch6"; + bus-interface-ahb1; + }; + hsitxch7@dmac0 { + signal = "hsitxch7"; + bus-interface-ahb1; + }; +};