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[209.132.180.67]) by mx.google.com with ESMTP id g3si5671248pdi.100.2014.09.02.05.03.17 for ; Tue, 02 Sep 2014 05:03:17 -0700 (PDT) Received-SPF: none (google.com: linux-leds-owner@vger.kernel.org does not designate permitted sender hosts) client-ip=209.132.180.67; Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753327AbaIBMDM (ORCPT ); Tue, 2 Sep 2014 08:03:12 -0400 Received: from mail-wg0-f47.google.com ([74.125.82.47]:42694 "EHLO mail-wg0-f47.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753225AbaIBMDK (ORCPT ); Tue, 2 Sep 2014 08:03:10 -0400 Received: by mail-wg0-f47.google.com with SMTP id z12so6771739wgg.30 for ; Tue, 02 Sep 2014 05:03:09 -0700 (PDT) X-Received: by 10.180.75.14 with SMTP id y14mr28474206wiv.79.1409659389219; Tue, 02 Sep 2014 05:03:09 -0700 (PDT) Received: from localhost.localdomain ([85.235.11.236]) by mx.google.com with ESMTPSA id hm5sm9125196wjb.2.2014.09.02.05.03.07 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 02 Sep 2014 05:03:08 -0700 (PDT) From: Linus Walleij To: linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-leds@vger.kernel.org, linux-pm@vger.kernel.org Cc: Arnd Bergmann , Pawel Moll , Mark Rutland , Marc Zyngier , Will Deacon , Rob Herring , Florian Fainelli , Linus Walleij Subject: [PATCH 6/8] ARM: l2c: parse 'cache-size' and 'cache-sets' properties Date: Tue, 2 Sep 2014 14:02:32 +0200 Message-Id: <1409659354-23553-7-git-send-email-linus.walleij@linaro.org> X-Mailer: git-send-email 1.9.3 In-Reply-To: <1409659354-23553-1-git-send-email-linus.walleij@linaro.org> References: <1409659354-23553-1-git-send-email-linus.walleij@linaro.org> Sender: linux-leds-owner@vger.kernel.org Precedence: list List-ID: X-Mailing-List: linux-leds@vger.kernel.org X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: linus.walleij@linaro.org X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.220.175 as permitted sender) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , From: Florian Fainelli When both 'cache-size' and 'cache-sets' are specified for a L2 cache controller node, parse those properties and make sure we validate the way_size based on which type of L2 cache controller we are using. Update the L2 cache controller Device Tree binding with the optional 'cache-size' and 'cache-sets' properties. Signed-off-by: Florian Fainelli Signed-off-by: Linus Walleij --- Documentation/devicetree/bindings/arm/l2cc.txt | 2 + arch/arm/mm/cache-l2x0.c | 61 ++++++++++++++++++++++++++ 2 files changed, 63 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/l2cc.txt b/Documentation/devicetree/bindings/arm/l2cc.txt index af527ee111c2..d33ed2344c7e 100644 --- a/Documentation/devicetree/bindings/arm/l2cc.txt +++ b/Documentation/devicetree/bindings/arm/l2cc.txt @@ -44,6 +44,8 @@ Optional properties: I/O coherent mode. Valid only when the arm,pl310-cache compatible string is used. - interrupts : 1 combined interrupt. +- cache-size : specifies the size in bytes of the cache +- cache-sets : specifies the number of associativity sets of the cache - cache-id-part: cache id part number to be used if it is not present on hardware - wt-override: If present then L2 is forced to Write through mode diff --git a/arch/arm/mm/cache-l2x0.c b/arch/arm/mm/cache-l2x0.c index 363c27bee3f6..c735f792c3d5 100644 --- a/arch/arm/mm/cache-l2x0.c +++ b/arch/arm/mm/cache-l2x0.c @@ -945,6 +945,61 @@ static int l2_wt_override; * pass it though the device tree */ static u32 cache_id_part_number_from_dt; +static void __init l2x0_cache_size_of_parse(const struct device_node *np, + u32 *aux_val, u32 *aux_mask, + u32 max_way_size) +{ + u32 mask = 0, val = 0; + u32 size = 0, sets = 0; + u32 way_size = 0, way_size_bits = 1; + + of_property_read_u32(np, "cache-size", &size); + of_property_read_u32(np, "cache-sets", &sets); + + if (!size || !sets) + return; + + way_size = size / sets; + + if (way_size > max_way_size) { + pr_warn("L2C: way size %dKB is too large\n", way_size >> 10); + return; + } + + way_size >>= 10; + switch (way_size) { + case 512: + way_size_bits = 6; + break; + case 256: + way_size_bits = 5; + break; + case 128: + way_size_bits = 4; + break; + case 64: + way_size_bits = 3; + break; + case 32: + way_size_bits = 2; + break; + case 16: + way_size_bits = 1; + break; + default: + pr_err("cache way size: %d KB is not mapped\n", + way_size); + break; + } + + mask |= L2C_AUX_CTRL_WAY_SIZE_MASK; + val |= (way_size_bits << L2C_AUX_CTRL_WAY_SIZE_SHIFT); + + *aux_val &= ~mask; + *aux_val |= val; + *aux_mask &= ~mask; +} + static void __init l2x0_of_parse(const struct device_node *np, u32 *aux_val, u32 *aux_mask) { @@ -974,6 +1029,8 @@ static void __init l2x0_of_parse(const struct device_node *np, val |= (dirty - 1) << L2X0_AUX_CTRL_DIRTY_LATENCY_SHIFT; } + l2x0_cache_size_of_parse(np, aux_val, aux_mask, SZ_256K); + *aux_val &= ~mask; *aux_val |= val; *aux_mask &= ~mask; @@ -1047,6 +1104,8 @@ static void __init l2c310_of_parse(const struct device_node *np, writel_relaxed((filter[0] & ~(SZ_1M - 1)) | L310_ADDR_FILTER_EN, l2x0_base + L310_ADDR_FILTER_START); } + + l2x0_cache_size_of_parse(np, aux_val, aux_mask, SZ_512K); } static const struct l2c_init_data of_l2c310_data __initconst = { @@ -1253,6 +1312,8 @@ static void __init aurora_of_parse(const struct device_node *np, *aux_val &= ~mask; *aux_val |= val; *aux_mask &= ~mask; + + l2x0_cache_size_of_parse(np, aux_val, aux_mask, SZ_256K); } static const struct l2c_init_data of_aurora_with_outer_data __initconst = {