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[2001:1868:205::9]) by mx.google.com with ESMTPS id pj9si9001605pac.234.2014.08.01.02.23.59 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 01 Aug 2014 02:23:59 -0700 (PDT) Received-SPF: none (google.com: linux-arm-kernel-bounces+patch=linaro.org@lists.infradead.org does not designate permitted sender hosts) client-ip=2001:1868:205::9; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1XD938-0008Mf-Cl; Fri, 01 Aug 2014 09:22:54 +0000 Received: from mail-pd0-f181.google.com ([209.85.192.181]) by bombadil.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1XD930-00081v-3Q for linux-arm-kernel@lists.infradead.org; Fri, 01 Aug 2014 09:22:46 +0000 Received: by mail-pd0-f181.google.com with SMTP id g10so5193129pdj.26 for ; Fri, 01 Aug 2014 02:22:25 -0700 (PDT) X-Received: by 10.68.87.101 with SMTP id w5mr4366556pbz.130.1406884945140; Fri, 01 Aug 2014 02:22:25 -0700 (PDT) Received: from localhost.localdomain ([114.97.106.113]) by mx.google.com with ESMTPSA id hu11sm12154305pdb.53.2014.08.01.02.22.19 for (version=TLSv1.1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Fri, 01 Aug 2014 02:22:24 -0700 (PDT) From: Zhangfei Gao To: Mike Turquette , haojian.zhuang@linaro.org, haifeng.yan@linaro.org, jchxue@gmail.com, xuwei5@hisilicon.com Subject: [PATCH v3 5/5] clk: hix5hd2: add the I2C clocks Date: Fri, 1 Aug 2014 17:21:14 +0800 Message-Id: <1406884874-30406-6-git-send-email-zhangfei.gao@linaro.org> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1406884874-30406-1-git-send-email-zhangfei.gao@linaro.org> References: <1406884874-30406-1-git-send-email-zhangfei.gao@linaro.org> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20140801_022246_187903_5CE9FD9D X-CRM114-Status: UNSURE ( 9.65 ) X-CRM114-Notice: Please train this message. X-Spam-Score: -1.4 (-) X-Spam-Report: SpamAssassin version 3.4.0 on bombadil.infradead.org summary: Content analysis details: (-1.4 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.7 RCVD_IN_DNSWL_LOW RBL: Sender listed at http://www.dnswl.org/, low trust [209.85.192.181 listed in list.dnswl.org] -0.0 SPF_PASS SPF: sender matches SPF record -0.7 RCVD_IN_MSPIKE_H2 RBL: Average reputation (+2) [209.85.192.181 listed in wl.mailspike.net] Cc: Wei Yan , linux-arm-kernel@lists.infradead.org X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.18-1 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: , List-Help: , List-Subscribe: , MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patch=linaro.org@lists.infradead.org X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: zhangfei.gao@linaro.org X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.220.169 as permitted sender) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 From: Wei Yan hix5hd2 add the I2C clocks (I2C0~i2C5) Signed-off-by: Wei Yan --- drivers/clk/hisilicon/clk-hix5hd2.c | 25 +++++++++++++++++++++++++ include/dt-bindings/clock/hix5hd2-clock.h | 12 ++++++++++++ 2 files changed, 37 insertions(+) diff --git a/drivers/clk/hisilicon/clk-hix5hd2.c b/drivers/clk/hisilicon/clk-hix5hd2.c index 21f32d9..3a84ea5 100644 --- a/drivers/clk/hisilicon/clk-hix5hd2.c +++ b/drivers/clk/hisilicon/clk-hix5hd2.c @@ -105,6 +105,31 @@ static struct hisi_gate_clock hix5hd2_gate_clks[] __initdata = { CLK_SET_RATE_PARENT, 0x48, 4, 0, }, { HIX5HD2_IR_RST, "rst_ir", "clk_ir", CLK_SET_RATE_PARENT, 0x48, 5, CLK_GATE_SET_TO_DISABLE, }, + /* I2C */ + {HIX5HD2_I2C0_CLK, "clk_i2c0", "100m", + CLK_SET_RATE_PARENT, 0x06c, 4, 0, }, + {HIX5HD2_I2C0_RST, "rst_i2c0", "clk_i2c0", + CLK_SET_RATE_PARENT, 0x06c, 5, CLK_GATE_SET_TO_DISABLE, }, + {HIX5HD2_I2C1_CLK, "clk_i2c1", "100m", + CLK_SET_RATE_PARENT, 0x06c, 8, 0, }, + {HIX5HD2_I2C1_RST, "rst_i2c1", "clk_i2c1", + CLK_SET_RATE_PARENT, 0x06c, 9, CLK_GATE_SET_TO_DISABLE, }, + {HIX5HD2_I2C2_CLK, "clk_i2c2", "100m", + CLK_SET_RATE_PARENT, 0x06c, 12, 0, }, + {HIX5HD2_I2C2_RST, "rst_i2c2", "clk_i2c2", + CLK_SET_RATE_PARENT, 0x06c, 13, CLK_GATE_SET_TO_DISABLE, }, + {HIX5HD2_I2C3_CLK, "clk_i2c3", "100m", + CLK_SET_RATE_PARENT, 0x06c, 16, 0, }, + {HIX5HD2_I2C3_RST, "rst_i2c3", "clk_i2c3", + CLK_SET_RATE_PARENT, 0x06c, 17, CLK_GATE_SET_TO_DISABLE, }, + {HIX5HD2_I2C4_CLK, "clk_i2c4", "100m", + CLK_SET_RATE_PARENT, 0x06c, 20, 0, }, + {HIX5HD2_I2C4_RST, "rst_i2c4", "clk_i2c4", + CLK_SET_RATE_PARENT, 0x06c, 21, CLK_GATE_SET_TO_DISABLE, }, + {HIX5HD2_I2C5_CLK, "clk_i2c5", "100m", + CLK_SET_RATE_PARENT, 0x06c, 0, 0, }, + {HIX5HD2_I2C5_RST, "rst_i2c5", "clk_i2c5", + CLK_SET_RATE_PARENT, 0x06c, 1, CLK_GATE_SET_TO_DISABLE, }, }; enum hix5hd2_clk_type { diff --git a/include/dt-bindings/clock/hix5hd2-clock.h b/include/dt-bindings/clock/hix5hd2-clock.h index 6aa4fec..025a8d9 100644 --- a/include/dt-bindings/clock/hix5hd2-clock.h +++ b/include/dt-bindings/clock/hix5hd2-clock.h @@ -64,6 +64,18 @@ #define HIX5HD2_WDG0_RST 140 #define HIX5HD2_IR_CLK 141 #define HIX5HD2_IR_RST 142 +#define HIX5HD2_I2C0_CLK 143 +#define HIX5HD2_I2C0_RST 144 +#define HIX5HD2_I2C1_CLK 145 +#define HIX5HD2_I2C1_RST 146 +#define HIX5HD2_I2C2_CLK 147 +#define HIX5HD2_I2C2_RST 148 +#define HIX5HD2_I2C3_CLK 149 +#define HIX5HD2_I2C3_RST 150 +#define HIX5HD2_I2C4_CLK 151 +#define HIX5HD2_I2C4_RST 152 +#define HIX5HD2_I2C5_CLK 153 +#define HIX5HD2_I2C5_RST 154 /* complex */ #define HIX5HD2_MAC0_CLK 192