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[109.148.232.149]) by mx.google.com with ESMTPSA id vl4sm37473793igb.3.2014.07.29.07.06.06 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 29 Jul 2014 07:06:08 -0700 (PDT) From: Lee Jones To: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Cc: lee.jones@linaro.org, kernel@stlinux.com, tglx@linutronix.de, jason@lakedaemon.net, devicetree@vger.kernel.org Subject: [PATCH 5/6] ARM: STi: STiH416: Enable PMU IRQs Date: Tue, 29 Jul 2014 15:05:43 +0100 Message-Id: <1406642744-22589-6-git-send-email-lee.jones@linaro.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1406642744-22589-1-git-send-email-lee.jones@linaro.org> References: <1406642744-22589-1-git-send-email-lee.jones@linaro.org> Sender: devicetree-owner@vger.kernel.org Precedence: list List-ID: X-Mailing-List: devicetree@vger.kernel.org X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: lee.jones@linaro.org X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.220.182 as permitted sender) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , This driver is used to enable System Configuration Register controlled External, CTI (Core Sight), PMU (Performance Management), and PL310 L2 Cache IRQs prior to use. Here we are enabling PMU IRQs on both channels. Signed-off-by: Lee Jones --- arch/arm/boot/dts/stih416.dtsi | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/arch/arm/boot/dts/stih416.dtsi b/arch/arm/boot/dts/stih416.dtsi index badefd6..7276125 100644 --- a/arch/arm/boot/dts/stih416.dtsi +++ b/arch/arm/boot/dts/stih416.dtsi @@ -11,6 +11,7 @@ #include "stih416-pinctrl.dtsi" #include #include +#include / { L2: cache-controller { compatible = "arm,pl310-cache"; @@ -27,6 +28,15 @@ interrupts = ; }; + irq-syscfg { + compatible = "st,stih416-irq-syscfg"; + st,syscfg = <&syscfg_cpu>; + st,irq-device = , + ; + st,fiq-device = , + ; + }; + soc { #address-cells = <1>; #size-cells = <1>;