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[2001:1868:205::9]) by mx.google.com with ESMTPS id f17si8907161pdm.64.2014.07.28.05.54.56 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 28 Jul 2014 05:54:56 -0700 (PDT) Received-SPF: none (google.com: linux-arm-kernel-bounces+patch=linaro.org@lists.infradead.org does not designate permitted sender hosts) client-ip=2001:1868:205::9; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1XBkRD-0002og-RX; Mon, 28 Jul 2014 12:53:59 +0000 Received: from mail-pa0-f46.google.com ([209.85.220.46]) by bombadil.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1XBkR0-0002JJ-Qz for linux-arm-kernel@lists.infradead.org; Mon, 28 Jul 2014 12:53:47 +0000 Received: by mail-pa0-f46.google.com with SMTP id lj1so10435529pab.19 for ; Mon, 28 Jul 2014 05:53:26 -0700 (PDT) X-Received: by 10.70.123.103 with SMTP id lz7mr32049869pdb.61.1406552006173; Mon, 28 Jul 2014 05:53:26 -0700 (PDT) Received: from localhost.localdomain ([61.172.253.147]) by mx.google.com with ESMTPSA id ia2sm17602248pbb.32.2014.07.28.05.53.16 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 28 Jul 2014 05:53:25 -0700 (PDT) From: Haojian Zhuang To: arnd@arndb.de, xuwei5@hisilicon.com, olof@lixom.net, khilman@linaro.org, arm@kernel.org, linux-arm-kernel@lists.infradead.org, yanhaifeng@hisilicon.com, liguozhu@hisilicon.com Subject: [PATCH v5 8/8] ARM: hisi: remove smp from machine descriptor Date: Mon, 28 Jul 2014 20:51:23 +0800 Message-Id: <1406551883-26154-9-git-send-email-haojian.zhuang@linaro.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1406551883-26154-1-git-send-email-haojian.zhuang@linaro.org> References: <1406551883-26154-1-git-send-email-haojian.zhuang@linaro.org> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20140728_055346_906170_47FEA7C5 X-CRM114-Status: GOOD ( 10.94 ) X-Spam-Score: -0.7 (/) X-Spam-Report: SpamAssassin version 3.4.0 on bombadil.infradead.org summary: Content analysis details: (-0.7 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.7 RCVD_IN_DNSWL_LOW RBL: Sender listed at http://www.dnswl.org/, low trust [209.85.220.46 listed in list.dnswl.org] -0.0 SPF_PASS SPF: sender matches SPF record -0.0 RCVD_IN_MSPIKE_H3 RBL: Good reputation (+3) [209.85.220.46 listed in wl.mailspike.net] -0.0 RCVD_IN_MSPIKE_WL Mailspike good senders Cc: Haojian Zhuang X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.18-1 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: , List-Help: , List-Subscribe: , MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patch=linaro.org@lists.infradead.org X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: haojian.zhuang@linaro.org X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.220.178 as permitted sender) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 Use CPU_METHOD_OF_DECLARE() instead. And declare smp method in dts file. Signed-off-by: Haojian Zhuang --- arch/arm/boot/dts/hi3620.dtsi | 1 + arch/arm/boot/dts/hix5hd2-dkb.dts | 1 + arch/arm/mach-hisi/hisilicon.c | 4 ---- arch/arm/mach-hisi/platsmp.c | 3 +++ 4 files changed, 5 insertions(+), 4 deletions(-) diff --git a/arch/arm/boot/dts/hi3620.dtsi b/arch/arm/boot/dts/hi3620.dtsi index ab1116d..ea6b0c1 100644 --- a/arch/arm/boot/dts/hi3620.dtsi +++ b/arch/arm/boot/dts/hi3620.dtsi @@ -33,6 +33,7 @@ cpus { #address-cells = <1>; #size-cells = <0>; + enable-method = "hisilicon,hi3xxx-smp"; cpu@0 { device_type = "cpu"; diff --git a/arch/arm/boot/dts/hix5hd2-dkb.dts b/arch/arm/boot/dts/hix5hd2-dkb.dts index 32c7fd1..556c98a 100644 --- a/arch/arm/boot/dts/hix5hd2-dkb.dts +++ b/arch/arm/boot/dts/hix5hd2-dkb.dts @@ -21,6 +21,7 @@ cpus { #address-cells = <1>; #size-cells = <0>; + enable-method = "hisilicon,hix5hd2-smp"; cpu@0 { compatible = "arm,cortex-a9"; diff --git a/arch/arm/mach-hisi/hisilicon.c b/arch/arm/mach-hisi/hisilicon.c index 284f9a1..2544d84 100644 --- a/arch/arm/mach-hisi/hisilicon.c +++ b/arch/arm/mach-hisi/hisilicon.c @@ -18,8 +18,6 @@ #include #include -#include "core.h" - #define HI3620_SYSCTRL_PHYS_BASE 0xfc802000 #define HI3620_SYSCTRL_VIRT_BASE 0xfe802000 @@ -57,7 +55,6 @@ DT_MACHINE_START(HI3620, "Hisilicon Hi3620 (Flattened Device Tree)") .dt_compat = hi3xxx_compat, .l2c_aux_val = 0x0, .l2c_aux_mask = 0xffffffff, - .smp = smp_ops(hi3xxx_smp_ops), MACHINE_END static const char *hix5hd2_compat[] __initconst = { @@ -69,5 +66,4 @@ DT_MACHINE_START(HIX5HD2_DT, "Hisilicon HIX5HD2 (Flattened Device Tree)") .dt_compat = hix5hd2_compat, .l2c_aux_val = 0x00050000, .l2c_aux_mask = 0xfff0ffff, - .smp = smp_ops(hix5hd2_smp_ops), MACHINE_END diff --git a/arch/arm/mach-hisi/platsmp.c b/arch/arm/mach-hisi/platsmp.c index ecf7058..cc377b6 100644 --- a/arch/arm/mach-hisi/platsmp.c +++ b/arch/arm/mach-hisi/platsmp.c @@ -131,3 +131,6 @@ struct smp_operations hix5hd2_smp_ops __initdata = { .cpu_die = hix5hd2_cpu_die, #endif }; + +CPU_METHOD_OF_DECLARE(hi3xxx_smp, "hisilicon,hi3xxx-smp", &hi3xxx_smp_ops); +CPU_METHOD_OF_DECLARE(hix5hd2_smp, "hisilicon,hix5hd2-smp", &hix5hd2_smp_ops);