From patchwork Fri Jul 18 15:14:27 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Murali Karicheri X-Patchwork-Id: 33873 Return-Path: X-Original-To: linaro@patches.linaro.org Delivered-To: linaro@patches.linaro.org Received: from mail-oi0-f70.google.com (mail-oi0-f70.google.com [209.85.218.70]) by ip-10-151-82-157.ec2.internal (Postfix) with ESMTPS id E6BFA208CF for ; Fri, 18 Jul 2014 15:16:43 +0000 (UTC) Received: by mail-oi0-f70.google.com with SMTP id u20sf6283220oif.5 for ; Fri, 18 Jul 2014 08:16:42 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:delivered-to:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:sender:precedence:list-id :x-original-sender:x-original-authentication-results:mailing-list :list-post:list-help:list-archive:list-unsubscribe:content-type; bh=SGQE/3R7DyZeEQJncMRd970VzMxsE5IWfQvYyap2DEk=; b=XSvHYbvsS/Ba4V9lIGBvyFORBeZhBBh2CfMD13czJVb/UTEmIHewmm94aB0s3qCG57 MBtiuMCqo0zUxtV+San7tBs8hZyS5EW+7SEbFCU6G38NE+RCRV1C9Fozn4TD3DDr5Bb2 r+1dWyFeZW6+DKBuacaHXv8x62Ov30Z2M9WWcWNxx8oJd1goXko3Rcn3u1al8mRjQv1M v13fw5MFZnNONJWBlm0vcNnPMYgUaEcJxa67lllmwPPoHLc4YlxiWlRxHpyVB6iHtV7D Zc7KFWPhdVDunoQO1a65wWSvaeoG2W3DrckEAP0y1yBCwkdklkRIsxX6F5tSsZpDv4tw MwFw== X-Gm-Message-State: ALoCoQnaiQtLFIrQuf9fpf//LadVRmw2XbQ99wfFjX2vJy6ABZhJdNTaFUdK6wRveUT62XHfncbQ X-Received: by 10.182.70.74 with SMTP id k10mr2684844obu.34.1405696602622; Fri, 18 Jul 2014 08:16:42 -0700 (PDT) X-BeenThere: patchwork-forward@linaro.org Received: by 10.50.43.234 with SMTP id z10ls383847igl.33.gmail; Fri, 18 Jul 2014 08:16:42 -0700 (PDT) X-Received: by 10.68.113.133 with SMTP id iy5mr5907592pbb.135.1405696602491; Fri, 18 Jul 2014 08:16:42 -0700 (PDT) Received: from mail-vc0-f171.google.com (mail-vc0-f171.google.com [209.85.220.171]) by mx.google.com with ESMTPS id df5si6031267vec.75.2014.07.18.08.16.32 for (version=TLSv1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Fri, 18 Jul 2014 08:16:32 -0700 (PDT) Received-SPF: pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.220.171 as permitted sender) client-ip=209.85.220.171; Received: by mail-vc0-f171.google.com with SMTP id hq11so6092727vcb.16 for ; Fri, 18 Jul 2014 08:16:32 -0700 (PDT) X-Received: by 10.52.244.138 with SMTP id xg10mr5785086vdc.40.1405696592034; Fri, 18 Jul 2014 08:16:32 -0700 (PDT) X-Forwarded-To: patchwork-forward@linaro.org X-Forwarded-For: patch@linaro.org patchwork-forward@linaro.org Delivered-To: patch@linaro.org Received: by 10.221.37.5 with SMTP id tc5csp19563vcb; Fri, 18 Jul 2014 08:16:31 -0700 (PDT) X-Received: by 10.68.132.42 with SMTP id or10mr6003495pbb.80.1405696581867; Fri, 18 Jul 2014 08:16:21 -0700 (PDT) Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id bk6si3156440pdb.110.2014.07.18.08.16.17; Fri, 18 Jul 2014 08:16:17 -0700 (PDT) Received-SPF: none (google.com: linux-kernel-owner@vger.kernel.org does not designate permitted sender hosts) client-ip=209.132.180.67; Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S965711AbaGRPQG (ORCPT + 24 others); Fri, 18 Jul 2014 11:16:06 -0400 Received: from arroyo.ext.ti.com ([192.94.94.40]:51674 "EHLO arroyo.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S965092AbaGRPQA (ORCPT ); Fri, 18 Jul 2014 11:16:00 -0400 Received: from dflxv15.itg.ti.com ([128.247.5.124]) by arroyo.ext.ti.com (8.13.7/8.13.7) with ESMTP id s6IFEXN8000515; Fri, 18 Jul 2014 10:14:33 -0500 Received: from DLEE70.ent.ti.com (dlemailx.itg.ti.com [157.170.170.113]) by dflxv15.itg.ti.com (8.14.3/8.13.8) with ESMTP id s6IFEXhE030900; Fri, 18 Jul 2014 10:14:33 -0500 Received: from dlep33.itg.ti.com (157.170.170.75) by DLEE70.ent.ti.com (157.170.170.113) with Microsoft SMTP Server id 14.3.174.1; Fri, 18 Jul 2014 10:14:33 -0500 Received: from localhost.localdomain (ileax41-snat.itg.ti.com [10.172.224.153]) by dlep33.itg.ti.com (8.14.3/8.13.8) with ESMTP id s6IFESYn025193; Fri, 18 Jul 2014 10:14:32 -0500 From: Murali Karicheri To: , , CC: Murali Karicheri , Santosh Shilimkar , Russell King , Grant Likely , Rob Herring , Jingoo Han , Bjorn Helgaas , Richard Zhu , Kishon Vijay Abraham I , Marek Vasut , Arnd Bergmann , Pawel Moll , Mark Rutland , Ian Campbell , Kumar Gala , Randy Dunlap Subject: [PATCH v6 3/5] PCI: designware: enhance dw_pcie_host_init() to support v3.65 DW hardware Date: Fri, 18 Jul 2014 11:14:27 -0400 Message-ID: <1405696469-7172-4-git-send-email-m-karicheri2@ti.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1405696469-7172-1-git-send-email-m-karicheri2@ti.com> References: <1405696469-7172-1-git-send-email-m-karicheri2@ti.com> MIME-Version: 1.0 Sender: linux-kernel-owner@vger.kernel.org Precedence: list List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: m-karicheri2@ti.com X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.220.171 as permitted sender) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , keystone PCI controller is based on v3.65 designware hardware. This version differs from newer versions of the hardware in few functional areas discussed below that makes it necessary to change dw_pcie_host_init() to support v3.65 based PCI controller. 1. No support for ATU port. So any ATU specific resource handling code is to be bypassed for v3.65 h/w. 2. MSI controller uses Application space to implement MSI and 32 MSI interrupts are multiplexed over 8 IRQs to the host. Hence the code to process MSI IRQ needs to be different. This patch allows platform driver to provide its own irq_domain_ops ptr to irq_domain_add_linear() through an API callback from the designware core driver. 3. MSI interrupt generation requires EP to write to the RC's application register. So enhance the driver to allow setup of inbound access to MSI irq register as a post scan bus API callback. Signed-off-by: Murali Karicheri Reviewed-by: Pratyush Anand Acked-by: Mohit KUMAR CC: Santosh Shilimkar CC: Russell King CC: Grant Likely CC: Rob Herring CC: Jingoo Han CC: Bjorn Helgaas CC: Richard Zhu CC: Kishon Vijay Abraham I CC: Marek Vasut CC: Arnd Bergmann CC: Pawel Moll CC: Mark Rutland CC: Ian Campbell CC: Kumar Gala CC: Randy Dunlap CC: Grant Likely --- drivers/pci/host/pcie-designware.c | 54 +++++++++++++++++++++++------------- drivers/pci/host/pcie-designware.h | 2 ++ 2 files changed, 36 insertions(+), 20 deletions(-) diff --git a/drivers/pci/host/pcie-designware.c b/drivers/pci/host/pcie-designware.c index 905941c..35bb4af 100644 --- a/drivers/pci/host/pcie-designware.c +++ b/drivers/pci/host/pcie-designware.c @@ -420,8 +420,8 @@ int __init dw_pcie_host_init(struct pcie_port *pp) struct device_node *np = pp->dev->of_node; struct of_pci_range range; struct of_pci_range_parser parser; + int i, ret; u32 val; - int i; if (of_pci_range_parser_init(&parser, np)) { dev_err(pp->dev, "missing ranges property\n"); @@ -467,21 +467,26 @@ int __init dw_pcie_host_init(struct pcie_port *pp) } } - pp->cfg0_base = pp->cfg.start; - pp->cfg1_base = pp->cfg.start + pp->config.cfg0_size; pp->mem_base = pp->mem.start; - pp->va_cfg0_base = devm_ioremap(pp->dev, pp->cfg0_base, - pp->config.cfg0_size); if (!pp->va_cfg0_base) { - dev_err(pp->dev, "error with ioremap in function\n"); - return -ENOMEM; + pp->cfg0_base = pp->cfg.start; + pp->va_cfg0_base = devm_ioremap(pp->dev, pp->cfg0_base, + pp->config.cfg0_size); + if (!pp->va_cfg0_base) { + dev_err(pp->dev, "error with ioremap in function\n"); + return -ENOMEM; + } } - pp->va_cfg1_base = devm_ioremap(pp->dev, pp->cfg1_base, - pp->config.cfg1_size); + if (!pp->va_cfg1_base) { - dev_err(pp->dev, "error with ioremap\n"); - return -ENOMEM; + pp->cfg1_base = pp->cfg.start + pp->config.cfg0_size; + pp->va_cfg1_base = devm_ioremap(pp->dev, pp->cfg1_base, + pp->config.cfg1_size); + if (!pp->va_cfg1_base) { + dev_err(pp->dev, "error with ioremap\n"); + return -ENOMEM; + } } if (of_property_read_u32(np, "num-lanes", &pp->lanes)) { @@ -490,16 +495,22 @@ int __init dw_pcie_host_init(struct pcie_port *pp) } if (IS_ENABLED(CONFIG_PCI_MSI)) { - pp->irq_domain = irq_domain_add_linear(pp->dev->of_node, - MAX_MSI_IRQS, &msi_domain_ops, - &dw_pcie_msi_chip); - if (!pp->irq_domain) { - dev_err(pp->dev, "irq domain init failed\n"); - return -ENXIO; - } + if (!pp->ops->msi_host_init) { + pp->irq_domain = irq_domain_add_linear(pp->dev->of_node, + MAX_MSI_IRQS, &msi_domain_ops, + &dw_pcie_msi_chip); + if (!pp->irq_domain) { + dev_err(pp->dev, "irq domain init failed\n"); + return -ENXIO; + } - for (i = 0; i < MAX_MSI_IRQS; i++) - irq_create_mapping(pp->irq_domain, i); + for (i = 0; i < MAX_MSI_IRQS; i++) + irq_create_mapping(pp->irq_domain, i); + } else { + ret = pp->ops->msi_host_init(pp, &dw_pcie_msi_chip); + if (ret < 0) + return ret; + } } if (pp->ops->host_init) @@ -759,6 +770,9 @@ static struct pci_bus *dw_pcie_scan_bus(int nr, struct pci_sys_data *sys) BUG(); } + if (bus && pp->ops->scan_bus) + pp->ops->scan_bus(pp); + return bus; } diff --git a/drivers/pci/host/pcie-designware.h b/drivers/pci/host/pcie-designware.h index 387f69e..080c649 100644 --- a/drivers/pci/host/pcie-designware.h +++ b/drivers/pci/host/pcie-designware.h @@ -70,6 +70,8 @@ struct pcie_host_ops { void (*msi_set_irq)(struct pcie_port *pp, int irq); void (*msi_clear_irq)(struct pcie_port *pp, int irq); u32 (*get_msi_data)(struct pcie_port *pp); + void (*scan_bus)(struct pcie_port *pp); + int (*msi_host_init)(struct pcie_port *pp, struct msi_chip *chip); }; int dw_pcie_cfg_read(void __iomem *addr, int where, int size, u32 *val);