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[2001:1868:205::9]) by mx.google.com with ESMTPS id re11si8663834pab.107.2014.07.09.23.57.17 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 09 Jul 2014 23:57:17 -0700 (PDT) Received-SPF: none (google.com: linux-arm-kernel-bounces+patch=linaro.org@lists.infradead.org does not designate permitted sender hosts) client-ip=2001:1868:205::9; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1X58H0-0003UD-E6; Thu, 10 Jul 2014 06:56:06 +0000 Received: from szxga01-in.huawei.com ([119.145.14.64]) by bombadil.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1X58G7-0001gs-LL for linux-arm-kernel@lists.infradead.org; Thu, 10 Jul 2014 06:55:13 +0000 Received: from 172.24.2.119 (EHLO SZXEML453-HUB.china.huawei.com) ([172.24.2.119]) by szxrg01-dlp.huawei.com (MOS 4.3.7-GA FastPath queued) with ESMTP id BYO22135; Thu, 10 Jul 2014 14:54:24 +0800 (CST) Received: from localhost (10.177.27.142) by SZXEML453-HUB.china.huawei.com (10.82.67.196) with Microsoft SMTP Server id 14.3.158.1; Thu, 10 Jul 2014 14:54:18 +0800 From: Zhen Lei To: Catalin Marinas , Will Deacon , linux-arm-kernel Subject: [PATCH v3 07/13] iommu/arm: Split arm_smmu_tlb_sync to reuse code Date: Thu, 10 Jul 2014 14:53:00 +0800 Message-ID: <1404975186-12032-8-git-send-email-thunder.leizhen@huawei.com> X-Mailer: git-send-email 1.8.4.msysgit.0 In-Reply-To: <1404975186-12032-1-git-send-email-thunder.leizhen@huawei.com> References: <1404975186-12032-1-git-send-email-thunder.leizhen@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.177.27.142] X-CFilter-Loop: Reflected X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20140709_235512_183640_8D310440 X-CRM114-Status: GOOD ( 13.38 ) X-Spam-Score: -1.4 (-) X-Spam-Report: SpamAssassin version 3.4.0 on bombadil.infradead.org summary: Content analysis details: (-1.4 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.7 RCVD_IN_DNSWL_LOW RBL: Sender listed at http://www.dnswl.org/, low trust [119.145.14.64 listed in list.dnswl.org] -0.0 RCVD_IN_MSPIKE_H3 RBL: Good reputation (+3) [119.145.14.64 listed in wl.mailspike.net] -0.0 SPF_PASS SPF: sender matches SPF record -0.7 RP_MATCHES_RCVD Envelope sender domain matches handover relay domain -0.0 RCVD_IN_MSPIKE_WL Mailspike good senders Cc: Zhen Lei X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.18-1 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: , List-Help: , List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patch=linaro.org@lists.infradead.org X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: thunder.leizhen@huawei.com X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.220.174 as permitted sender) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 TLB sync wait is a common operation, should be shared by all SMMUs. Signed-off-by: Zhen Lei --- drivers/iommu/arm-smmu-base.c | 15 +++++++++++++++ drivers/iommu/arm-smmu.c | 23 ++++++++++++----------- drivers/iommu/arm-smmu.h | 3 +++ 3 files changed, 30 insertions(+), 11 deletions(-) -- 1.8.0 diff --git a/drivers/iommu/arm-smmu-base.c b/drivers/iommu/arm-smmu-base.c index 4d1c511..53f7907 100644 --- a/drivers/iommu/arm-smmu-base.c +++ b/drivers/iommu/arm-smmu-base.c @@ -187,6 +187,21 @@ void __arm_smmu_free_bitmap(unsigned long *map, int idx) clear_bit(idx, map); } +void arm_smmu_tlb_sync_wait(struct arm_smmu_device *smmu) +{ + int count = 0; + + while (!smmu->hwdep_ops->tlb_sync_finished(smmu)) { + cpu_relax(); + if (++count == TLB_LOOP_TIMEOUT) { + dev_err_ratelimited(smmu->dev, + "TLB sync timed out -- SMMU may be deadlocked\n"); + return; + } + udelay(1); + } +} + void arm_smmu_flush_pgtable(struct arm_smmu_device *smmu, void *addr, size_t size) { diff --git a/drivers/iommu/arm-smmu.c b/drivers/iommu/arm-smmu.c index d2fc14c..fa65c7c 100644 --- a/drivers/iommu/arm-smmu.c +++ b/drivers/iommu/arm-smmu.c @@ -223,23 +223,23 @@ #define FSYNR0_WNR (1 << 4) +static int arm_smmu_tlb_sync_finished(struct arm_smmu_device *smmu) +{ + u32 reg; + void __iomem *gr0_base = ARM_SMMU_GR0(smmu); + + reg = readl_relaxed(gr0_base + ARM_SMMU_GR0_sTLBGSTATUS); + + return !(reg & sTLBGSTATUS_GSACTIVE); +} + /* Wait for any pending TLB invalidations to complete */ static void arm_smmu_tlb_sync(struct arm_smmu_device *smmu) { - int count = 0; void __iomem *gr0_base = ARM_SMMU_GR0(smmu); writel_relaxed(0, gr0_base + ARM_SMMU_GR0_sTLBGSYNC); - while (readl_relaxed(gr0_base + ARM_SMMU_GR0_sTLBGSTATUS) - & sTLBGSTATUS_GSACTIVE) { - cpu_relax(); - if (++count == TLB_LOOP_TIMEOUT) { - dev_err_ratelimited(smmu->dev, - "TLB sync timed out -- SMMU may be deadlocked\n"); - return; - } - udelay(1); - } + arm_smmu_tlb_sync_wait(smmu); } static void arm_smmu_tlb_inv_context(struct arm_smmu_cfg *cfg) @@ -869,6 +869,7 @@ static int arm_smmu_device_unload(struct arm_smmu_device *smmu) } static struct smmu_hwdep_ops arm_smmu_hwdep_ops = { + .tlb_sync_finished = arm_smmu_tlb_sync_finished, .tlb_inv_context = arm_smmu_tlb_inv_context, .context_fault = arm_smmu_context_fault, .global_fault = arm_smmu_global_fault, diff --git a/drivers/iommu/arm-smmu.h b/drivers/iommu/arm-smmu.h index 190f77c..8332ff0 100644 --- a/drivers/iommu/arm-smmu.h +++ b/drivers/iommu/arm-smmu.h @@ -209,6 +209,7 @@ struct arm_smmu_domain { /** * struct smmu_hwdep_ops - smmu hardware dependent ops + * @tlb_sync_finished: check whether tlb sync operation is finished * @tlb_inv_context: invalid smmu context bank tlb * @context_fault: context fault handler * @global_fault: global fault handler @@ -221,6 +222,7 @@ struct arm_smmu_domain { * @device_remove: turn off a smmu and reclaim associated resources */ struct smmu_hwdep_ops { + int (*tlb_sync_finished)(struct arm_smmu_device *smmu); void (*tlb_inv_context)(struct arm_smmu_cfg *cfg); irqreturn_t (*context_fault)(int irq, void *dev); irqreturn_t (*global_fault)(int irq, void *dev); @@ -237,6 +239,7 @@ struct smmu_hwdep_ops { extern int __arm_smmu_alloc_bitmap(unsigned long *map, int start, int end); extern void __arm_smmu_free_bitmap(unsigned long *map, int idx); +extern void arm_smmu_tlb_sync_wait(struct arm_smmu_device *smmu); extern struct arm_smmu_device *find_parent_smmu(struct arm_smmu_device *smmu); extern void arm_smmu_flush_pgtable(struct arm_smmu_device *smmu, void *addr, size_t size);