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[2001:1868:205::9]) by mx.google.com with ESMTPS id by7si8239849pdb.345.2014.07.09.23.57.07 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 09 Jul 2014 23:57:08 -0700 (PDT) Received-SPF: none (google.com: linux-arm-kernel-bounces+patch=linaro.org@lists.infradead.org does not designate permitted sender hosts) client-ip=2001:1868:205::9; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1X58Gl-0003Jf-Cl; Thu, 10 Jul 2014 06:55:51 +0000 Received: from szxga01-in.huawei.com ([119.145.14.64]) by bombadil.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1X58G7-0001hW-L4 for linux-arm-kernel@lists.infradead.org; Thu, 10 Jul 2014 06:55:13 +0000 Received: from 172.24.2.119 (EHLO szxeml462-hub.china.huawei.com) ([172.24.2.119]) by szxrg01-dlp.huawei.com (MOS 4.3.7-GA FastPath queued) with ESMTP id BYO22157; Thu, 10 Jul 2014 14:54:32 +0800 (CST) Received: from localhost (10.177.27.142) by szxeml462-hub.china.huawei.com (10.82.67.205) with Microsoft SMTP Server id 14.3.158.1; Thu, 10 Jul 2014 14:54:23 +0800 From: Zhen Lei To: Catalin Marinas , Will Deacon , linux-arm-kernel Subject: [PATCH v3 13/13] documentation/iommu: Add description of Hisilicon SMMU private binding Date: Thu, 10 Jul 2014 14:53:06 +0800 Message-ID: <1404975186-12032-14-git-send-email-thunder.leizhen@huawei.com> X-Mailer: git-send-email 1.8.4.msysgit.0 In-Reply-To: <1404975186-12032-1-git-send-email-thunder.leizhen@huawei.com> References: <1404975186-12032-1-git-send-email-thunder.leizhen@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.177.27.142] X-CFilter-Loop: Reflected X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20140709_235512_162795_8ECF03B6 X-CRM114-Status: UNSURE ( 7.38 ) X-CRM114-Notice: Please train this message. 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X-Original-Sender: thunder.leizhen@huawei.com X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.220.175 as permitted sender) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 This patch adds a description of private properties for the Hisilicon System MMU architecture. Signed-off-by: Zhen Lei --- Documentation/devicetree/bindings/iommu/arm,smmu.txt | 2 ++ drivers/iommu/arm-smmu-base.c | 3 +++ 2 files changed, 5 insertions(+) -- 1.8.0 diff --git a/Documentation/devicetree/bindings/iommu/arm,smmu.txt b/Documentation/devicetree/bindings/iommu/arm,smmu.txt index f284b99..23035ce 100644 --- a/Documentation/devicetree/bindings/iommu/arm,smmu.txt +++ b/Documentation/devicetree/bindings/iommu/arm,smmu.txt @@ -1,4 +1,5 @@ * ARM System MMU Architecture Implementation +* Hisilicon System MMU Architecture Implementation ARM SoCs may contain an implementation of the ARM System Memory Management Unit Architecture, which can be used to provide 1 or 2 stages @@ -15,6 +16,7 @@ conditions. "arm,smmu-v2" "arm,mmu-400" "arm,mmu-500" + "hisilicon,smmu-v1" depending on the particular implementation and/or the version of the architecture implemented. diff --git a/drivers/iommu/arm-smmu-base.c b/drivers/iommu/arm-smmu-base.c index d71af43..a0d7c6f 100644 --- a/drivers/iommu/arm-smmu-base.c +++ b/drivers/iommu/arm-smmu-base.c @@ -22,6 +22,9 @@ * - 4k and 64k pages, with contiguous pte hints. * - Up to 42-bit addressing (dependent on VA_BITS) * - Context fault reporting + * + * Additional supports: + * - Hisilicon smmu-v1 implementation */ #define pr_fmt(fmt) "arm-smmu: " fmt